- Silvus Technologies (Los Angeles, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Google (Mountain View, CA)
- RTL Design Engineer , Multimedia and Machine Learning Accelerators _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, ... Property (IP)(Camera, Display or COdec) or Machine Learning IP. + Experience with ASIC design methodologies for clock domain checks and reset checks. +… more
- Silvus Technologies (Irvine, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Lockheed Martin (Littleton, CO)
- …- - - **Key activities you will accomplish in this role:** * Support the primary design engineer with any power design activities that will be required for ... ** where you will be able to support lead engineer \(s\) in the potential design and development,...layout oversight * Parts selection * Flow FPGA or ASIC design requirements to ASIC /FPGA… more
- Amazon (Cupertino, CA)
- …learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server ... in TCL, Perl, and/or Python - Solid understanding of ASIC physical design , physical design ...and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven… more
- NVIDIA (Santa Clara, CA)
- …analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification , logic synthesis, timing ... Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement...teams at NVIDIA. + Work closely with software, architecture, design , verification , and silicon validation teams. +… more
- Micron Technology, Inc. (Boise, ID)
- …to learn, communicate and advance faster than ever. Job Description As an Electrical Design Engineer intern in the Systems Integration Group (SIG) of Micron ... LTspice, Cadence PSpice, or other electronic circuit simulation tools. * Experience with FPGA/ ASIC design HDL (Verilog/VHDL and System Verilog) * Knowledge of… more
- Micron Technology, Inc. (Boise, ID)
- …the world to learn, communicate and advance faster than ever. As an Electrical Design Engineer intern in the Systems Integration Group (SIG) of Micron ... Cadence PSpice, or other electronic circuit simulation tools. + Experience with FPGA/ ASIC design HDL (Verilog/VHDL and System Verilog) + Knowledge ofcommon… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from you! We are looking ... for a Senior Mask Layout Design Engineer , someone who is excited to...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more