- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from you! We are looking ... for a Senior Mask Layout Design Engineer , someone who is excited to...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops… more
- Microsoft Corporation (Mountain View, CA)
- …engineers to help achieve that mission. We are looking for a **Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... Throughout the program you will be interacting with various teams, including architecture, verification , and physical design , ensuring that the design is… more
- Silvus Technologies (Irvine, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA/RTL Design Engineer_** who will report to the _Director of FPGA Engineering_ on the ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Broadcom (Irvine, CA)
- …synthesis, etc. + prepare block level resource requirements & development schedule + generate verification & test plans for design validation + Perform design ... manufacturing. + Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or...Python, and C. + Experience with High-level Synthesis in design and verification is a plus. +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different memory interface standards to ... teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal… more
- Broadcom (Broomfield, CO)
- …+ Hands on experience with timing analysis and place and route tools for ASIC / SoC Design is a must. **Additional Requirements:** + Good problem solver. ... Sign-In before you apply.** **Job Description:** **Responsibilities Include:** + Work on Design Implementation activities related to place and route and/ or timing… more
- Northrop Grumman (Jessup, MD)
- …and supporting validation at the system level. + Experience with ASIC Specification generation and verification . + Multi-Disciplinary Engineering exposure ... within the Northrop Grumman Microelectronics Center (NGMC). Boasting state-of-the-art design capabilities, multiple processing nodes, electrical testing, environmental and… more
- Broadcom (Irvine, CA)
- …synthesis, etc. prepare block level resource requirements & development schedule generate verification & test plans for design validation Perform design ... Layer Products for High Speed Optical Communication. architect block level design specifications from the marketing requirements and/or system requirements prepare… more