• Electronics Engineer , Avionics Design

    Lockheed Martin (King Of Prussia, PA)
    …Design Engineer Electronics Power Engineer Electrical/Electronics Integration & Test Engineer ASIC / FPGA Engineer Component Engineer Analog ... **Description:** Join Our Team as a Circuit Design Engineer where you will work on the development of a sophisticated state\-of\-the\-art avionics product in a world… more
    Lockheed Martin (10/01/25)
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  • Hardware Engineer 2 - 23339 (FS Poly…

    Huntington Ingalls Industries (Fort Meade, MD)
    …with signal protocol analysis (RS232, CAN, PCIe, Gigabit serial, etc.) * Are proficient with ASIC , FPGA , or SOC design tools (Quartus, Vivado, ISE, etc.) * Are ... the team by utilizing in-house software tools to reverse engineer hardware assets provided by the US government. During...asset systems. + The use of HII proprietary tools, FPGA vendor tools, and third-party EDA tools will be… more
    Huntington Ingalls Industries (08/16/25)
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  • Hardware Engineer 3

    Huntington Ingalls Industries (Redstone Arsenal, AL)
    …with signal protocol analysis (RS232, CAN, PCIe, Gigabit serial, etc.) * Are proficient with ASIC , FPGA , or SOC design tools (Quartus, Vivado, ISE, etc.) * Are ... the team by utilizing in-house software tools to reverse engineer hardware assets provided by the US government. During...of asset systems. The use of HII proprietary tools, FPGA vendor tools, and third-party EDA tools will be… more
    Huntington Ingalls Industries (07/29/25)
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  • R&D Engineer Hardware

    Broadcom (Irvine, CA)
    …you apply.** **Job Description:** We are currently seeking a highly motivated engineer to join our talented Hardware Systems Team to design development platforms ... for the test and validation of custom mixed signal ASIC 's. The role will encompass the full development platform cycle starting from design concept based on… more
    Broadcom (09/26/25)
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  • Digital Design Engineer

    Meta (Austin, TX)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
    Meta (10/05/25)
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  • Digital IC Design Engineer

    Medtronic (Mounds View, MN)
    …compassionate world. **A Day in the Life** We have a great opportunity for an experienced ASIC / FPGA Digital Design Engineer with RTL experience in Verilog ... or VHDL - System Verilog preferred. Our Digital Designers also support verification and lab characterization. Put your skills using UVM, C, and Python to the test!… more
    Medtronic (10/14/25)
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  • Staff Hardware Systems Design Engineer

    Google (Sunnyvale, CA)
    …with Product teams to ensure that goals are met with systems and will work with ASIC / FPGA , Software, and Verification teams to ensure proper verification ... Staff Hardware Systems Design Engineer , Board and Systems _corporate_fare_ Google _place_ Sunnyvale,...SPI, etc. **About the job** As a Staff Hardware Engineer , you will work on Machine Learning/AI hardware systems… more
    Google (09/30/25)
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  • Hardware Engineer , Platforms, University…

    Google (Sunnyvale, CA)
    …Signal Integrity etc.) to design the desired product. You will also work with ASIC / FPGA , software, and verification teams to ensure proper verification ... Hardware Engineer , Platforms, University Graduate _corporate_fare_ Google _place_ Sunnyvale,...delivering unparalleled performance, efficiency, and integration. As a Hardware Engineer in the board and system design team, you… more
    Google (09/26/25)
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  • Senior Component Engineer

    Palo Alto Networks (Santa Clara, CA)
    …is a huge plus. + Demonstrated broad technical competence in multiple technologies ( ASIC , FPGA , Comm IC, Processor, SSD) with expert level experience in ... **Your Career** We are seeking an experienced and highly motivated Senior Component Engineer to join our exciting, fast growing company and reports to the Director… more
    Palo Alto Networks (10/16/25)
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  • Senior Applications Engineer - DDR Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6* Perl/Python Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob...RTL design in Verilog, System Verilog and FPGA design* Knowledge of AXI, DFI protocols* Working knowledge… more
    Cadence Design Systems, Inc. (10/11/25)
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