• Sr. ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …quality RTL -Ensure quality by running and tracking results of front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and ... / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an equal opportunity employer and does not… more
    Amazon (10/18/25)
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  • Analog/ ASIC , Account Technical Executive

    Cadence Design Systems, Inc. (Irvine, CA)
    …knowledge and understanding of custom/analog and mixed signal flows, and/or Digital implementation flows ( synthesis , place & route and signoff) and/or experience ... of the core technology requirements in the custom/analog and digital implementation and/or functional/formal verification space, coordination of sales strategies and… more
    Cadence Design Systems, Inc. (11/20/25)
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  • Design Implementation Engineer

    Broadcom (Allentown, PA)
    …Candidate will work closely with the IP and SOC design teams to enable block and ASIC level timing closure. + The engineer will work with the internal ASIC ... you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to complex digital and mixed signal IP blocks used… more
    Broadcom (11/20/25)
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  • Design Implementation Engineer

    Broadcom (Broomfield, CO)
    …you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure - ... floor-planning, partitioning, placement, clock tree synthesis , route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able to drive tools… more
    Broadcom (11/20/25)
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  • Design Automation DFT Engineer

    Broadcom (Fort Collins, CO)
    …Account, please Sign-In before you apply.** **Job Description:** **DFT Design Automation Engineer ** Broadcom's ASIC Products Division is seeking a Design ... Automation Software Development Engineer in the Design For Test (DFT) team developing...products and usage methodology to a world-wide, cutting edge, ASIC DFT technology development and implementation team.… more
    Broadcom (11/20/25)
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  • Physical Design Engineer I (Co-op) - United…

    Cisco (Maynard, MA)
    …The engineers work with technologies that involve the latest submicron technologies. An ASIC PD engineer would be involved in developing and optimizing physical ... floorplan and their implementation . Your Impact The Physical Design Engineer ...to understand the design architecture to ensure optimal physical implementation . Gate level netlist synthesis (physical… more
    Cisco (11/18/25)
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  • Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... Proficient in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design, and methodologies including synthesis , place and… more
    Amazon (10/25/25)
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  • Sr. Physical Design Engineer , Annapurna…

    Amazon (Austin, TX)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... for physical design closure - Drive IO/Core block physical implementation through synthesis , floor planning, bus /...MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm,… more
    Amazon (09/02/25)
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  • Senior FPGA Design Engineer (Hybrid-Puerto…

    RTX Corporation (Aguadilla, PR)
    …our mission today. This position is for a motivated Electrical or Computer Engineer to be involved in the design, implementation , verification, and integration ... blocks using VHDL or System Verilog. + Proficiency using ASIC and/or FPGA simulation and synthesis tools...Proficiency using ASIC and/or FPGA simulation and synthesis tools (eg Modelsim, Synplify, Quartus, Vivado, or other… more
    RTX Corporation (10/18/25)
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  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …initial floor plan. 5). Develop Verilog RTL. design verification support, logic synthesis , physical implementation constraints, static timing analysis. 6). Work ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...directly with the physical implementation team from initial floor planning to final timing… more
    Broadcom (11/19/25)
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