- Meta (Sunnyvale, CA)
- …prior to joining Meta 8. 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration 10. Experience ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan development… more
- NVIDIA (Santa Clara, CA)
- Are you passionate about DGX system connecting multiple ASIC chips together and FPGA prototyping? Are you interested in pushing the boundaries of innovation to make ... We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa...RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and route. + Improve performance of… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The… more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
- Broadcom (Fort Collins, CO)
- …Description:** Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering ... **Role Overview** This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands-on experience with the latest 5… more
- Amazon (Austin, TX)
- …tool decisions. - Experience in high-performance, low-power physical design, and implementation techniques with industry standard synthesis , PnR, or Signoff ... our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud...years in developing design methodology or CAD flows in synthesis , PNR, or sign-off areas for advanced technology nodes.… more
- Silvus Technologies (Los Angeles, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA Engineering_ on ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and work ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- NVIDIA (Hillsboro, OR)
- …is responsible to our environment. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip ... We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased...to build complex chips and interact directly with unit-level ASIC , Physical Design, CAD, Package Design, Software, DFT and… more
- Actalent (Herndon, VA)
- …Clearance* Job Description We are seeking a FPGA/ ASIC Design Engineer responsible for the architecture, implementation , and verification/validation through ... experience. + 5+ years of experience in implementing complex algorithms targeting ASIC /FPGAs. + Proficiency in VHDL and FPGA design/debug using Xilinx FPGA/Vivado. +… more