• Senior Principal ASIC Static Timing…

    Northrop Grumman (Linthicum Heights, MD)
    …or propose changes to fix them + Work closely with design , verification, design -for-test and physical design teams to optimize the timing and improve ... + 4 years of experience in the full product life cycle of ASIC Design **Preferred Qualifications:** + Master's Degree in Electrical or Computer Engineering +… more
    Northrop Grumman (11/13/25)
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  • ASIC Verification - Team Lead

    Microsoft Corporation (Santa Clara, CA)
    …software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to ... its integrated design , this solution empowers teams to operate with increased...information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or… more
    Microsoft Corporation (12/20/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …impact in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at ... inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our...is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
    NVIDIA (11/12/25)
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  • ASIC DFT DV Technical Leader

    Cisco (San Jose, CA)
    …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (12/13/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    …member of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to ... movement and low power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL… more
    NVIDIA (12/16/25)
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  • Senior DSP and ASIC Engineer

    Broadcom (Irvine, CA)
    …+ Demonstrate the ability to work through technology challenges and physical implementation issues associated with high-performance design implementations. + ... Sign-In before you apply.** **Job Description:** Looking for a design engineer to work on challenging high speed ...design engineer to work on challenging high speed design of complex modules for Ethernet and PCIE cores… more
    Broadcom (11/15/25)
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  • Summer 2026 Intern - ASIC Verification…

    Western Digital (Roseville, CA)
    …in an exciting career opportunity! **Minimum Requirements:** + Familiar with digital design , design verification, and gate-level simulation. + Familiar with ... orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected… more
    Western Digital (11/25/25)
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  • ASIC Reliability Engineer

    Cisco (San Jose, CA)
    …this highly visible role, you'll partner with teams across design , manufacturing, suppliers, and leadership-communicating clearly, navigating complex technical ... solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security,… more
    Cisco (12/13/25)
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  • Sr Advanced IC CAD Engineer

    Honeywell (Phoenix, AZ)
    Design platform needs spanning IC Design cell development, macrocell development, ASIC design systems, physical verification and mask-CAD flows. **WE ... and fostering an inclusive culture. **KEY RESPONSIBILITIES** + Work with IC Design EDA Applications, High Performance Compute cluster staff, and IC Design more
    Honeywell (11/14/25)
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  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...working on initial floor plan. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation… more
    Broadcom (11/19/25)
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