- Broadcom (Broomfield, CO)
- …+ Hands on experience with timing analysis and place and route tools for ASIC / SoC Design is a must. **Additional Requirements:** + Good problem solver. + ... timing closure - floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). +… more
- Insight Global (Santa Clara, CA)
- … team, driving strategy and execution across multiple projects. They will own the full ASIC physical design flow from RTL handoff to GDSII, including ... Skills and Requirements . Expertise in multiple areas of physical design , timing , and signoff . Strong scripting and… more
- Cisco (Maynard, MA)
- …and Synplify(R) synthesis tools for FPGAs * Expertise in creating FPGA implementations from ASIC RTL code * Expertise in digital design of standard cell ASICs ... manufacturing teams. **Your Impact** You are a high-energy FGPA Design engineer who loves to work on complex communications...Development and Automation * Contribute to FPGA Emulation of ASIC Blocks * Contribute to our custom ASIC… more
- Broadcom (San Jose, CA)
- …for, but not limited to, the following job duties: + Work as part of a physical design team implementing chips from netlist to GDSii with good understanding of ... Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC /Layout Design Engineer: Oversees definition, design...as tcl, perl and python. Write scripts to automate physical design flow and make it more… more
- Google (Sunnyvale, CA)
- SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior ... equivalent practical experience. + 4 years of experience with physical design . + Experience in physical...complex SoC. + Experience with multiple-cycles of SoC in ASIC design . + Experience with scripting languages… more
- Broadcom (San Jose, CA)
- …+ Testplan reviews, assertions, debugging, code and functional coverage + Floor plan, timing , congestion resolution with Physical Design team + Post ... Group at Broadcom has brought some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market. The group develops ASIC 's for L2/L3… more
- Emerson (Austin, TX)
- …an immediate opening for a Principal Digital Hardware Engineer within our talented hardware design team in Austin, TX. In this role, you will have the opportunity to ... will have opportunities to continue to expand your digital design skills by learning from experienced technical leaders and...THAT SET YOU APART:** + Familiarity with FPGA or ASIC integration into digital designs. + Experience in mixed-signal… more
- Broadcom (Fort Collins, CO)
- …self-test (BIST). + General knowledge of semiconductor technology and ASIC design flow including Verilog simulation and timing analysis. Verilog experience ... ASIC customers on their custom silicon products during design , bring-up, as well as debugging performance or HBM...+ Work with HBM suppliers as well as Broadcom's physical analysis teams as necessary to pinpoint failures. +… more
- Silvus Technologies (Los Angeles, CA)
- …using Verilog and System-Verilog. + Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or ... OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer- Signal Processing_** who will report to the...+ Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS… more
- Silvus Technologies (Irvine, CA)
- …using Verilog and System-Verilog. * Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or ... career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and… more