- Google (Austin, TX)
- …+ Perform logic synthesis, static timing analysis (STA), and work with physical design teams to achieve timing closure, power optimization, and ... years of experience in program management. + Experience in ASIC /chip design with leadership and technical ownership....automation of design flows. + Knowledge of physical design concepts (eg, floor planning, place… more
- Amazon (Redmond, WA)
- …Create and release FPGAs through the development phases of uArchitecture-RTL Design - Physical Implementation- Timing Closure-Simulation Validation- Lab Based ... degree in Electrical Engineering or a related field - Experience with modern ASIC /FPGA design and verification tools - Experience in writing test scripts… more
- Cisco (Milpitas, CA)
- …5+ years of experience with a Bachelors' degree. Experience expected to be in ASIC /FPGA design . + Proficiency in end-to-end FPGA development process. + Hands-on ... We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to...large, resource-intensive blocks (eg, DSP pipelines, memory controllers). + Timing Closure: Independently apply and analyze timing … more
- Fujifilm (Bothell, WA)
- …+ Create and release FPGAs through the development phases of Architecture, RTL Design , Physical Implementation, Timing Closure, Simulation Validation, Lab ... relevant industry experience or MS electrical engineering + Experience with FPGA/ ASIC design software (Altera and/or Xilinx) + Experience with VHDL preferred,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for-Test (DFT), Place & Route and Static Timing Analysis (STA).You ... ideal for someone with several years of hands on ASIC /IC design experience who is looking for...tools Or Cadence or Synopsys place and route tools ( Physical Synthesis, PnR, CTS, Static Timing Analysis)… more
- Amazon (Austin, TX)
- …in interconnect & transistor fundamentals in deep sub-micron processes - Understanding of ASIC Physical Design from RTL-to-GDSII - Understanding of other ... with product engineers, signal & power integrity engineers and physical design experts - defining best practices,...sign-off activities (ir/em, physical verification, timing closure, DFT) - 3+… more
- Honeywell (Phoenix, AZ)
- …Design platform needs spanning IC Design cell development, macrocell development, ASIC design systems, physical verification and mask-CAD flows. **WE ... and fostering an inclusive culture. **KEY RESPONSIBILITIES** + Work with IC Design EDA Applications, High Performance Compute cluster staff, and IC Design… more
- Cisco (Milpitas, CA)
- …hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various ... for the various boards. You will interface with Diagnostics, Software, Board design , Manufacturing and Hardware Qualification teams to ensure smooth delivery of the… more
- Amazon (Austin, TX)
- …As a Systems Engineer, this role is primarily responsible for the design , development and integration of communication payload and customer terminal systems. The ... generators / spectrum analyzers and use these to verify timing budgets. * Architect and document time/frequency/space acquisition and...attenuators etc. * Unblock themselves with reaching out RF, ASIC , SW, Comsys, Testbed teams to move forward in… more