• Senior System SW Engineer , System…

    Palo Alto Networks (Santa Clara, CA)
    …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and ... will also do hands-on coding, including: + Prototyping and modeling of new architectures and designs + Architectural models, test infrastructure, pre- and… more
    Palo Alto Networks (09/19/25)
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  • FPGA Engineer III

    Fujifilm (Bothell, WA)
    …Experience with simulators (Mentor Modelism desired) + Demonstrate proficiencies with FPGA/ ASIC verification tools, languages and methodologies + VHDL/Verilog, ... **Position Overview** As an FPGA Engineer III, you will be responsible for implementing...external experts and vendors to understand, integrate and implement new enabling technologies. To be successful in this role… more
    Fujifilm (10/11/25)
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  • Firmware Engineer IV

    Textron (Hunt Valley, MD)
    **Firmware Engineer IV** **Description** **_Who We Are_** Textron Systems is part of Textron, a $14 billion, multi\-industry company employing 35,000 talented ... This Role_** Textron Systems is seeking an experienced Firmware Engineer to join our team\. This individual will work...emerging program\. The individual will be responsible for developing new FPGA designs with an emphasis on simulation and… more
    Textron (09/05/25)
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  • Firmware Engineer IV

    Textron (Wilmington, MA)
    **Firmware Engineer IV** **Description** **_Who We Are_** Textron Systems is part of Textron, a $14 billion, multi\-industry company employing 35,000 talented ... This Role_** Textron Systems is seeking an experienced Firmware Engineer to join our team\. This individual will work...emerging program\. The individual will be responsible for developing new FPGA designs with an emphasis on simulation and… more
    Textron (08/07/25)
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  • Hardware Modeling Engineer

    Cisco (San Jose, CA)
    …enhancing simulation accuracy, performance, and multi-functional collaboration. + Work closely with ASIC design and verification teams from initial definition to ... Hardware Modeling Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441704) + Location:San Jose, California, US...now part of Cisco, is the heart of Cisco's ASIC design group. You'll be part of our team… more
    Cisco (10/13/25)
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  • Design Engineer Architect/Lead

    Broadcom (Fort Collins, CO)
    … physical design 12+ years of experience w/ a deep understanding of ASIC architecture, design, development and verification . - Significant experience with ... to aid in overall closure and manufacture of the ASIC with emphasis on low power, optimized area, max....**Supervision:** Acts independently to determine methods and procedures on new or special assignments. Will supervise the activities of… more
    Broadcom (09/10/25)
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  • Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ... job responsibilities Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes Drive… more
    Amazon (07/26/25)
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  • Software Engineer I

    Cadence Design Systems, Inc. (San Jose, CA)
    …and enable the products. We are now looking for a hands-on system integration engineer who wants to expand his/her scope, work with the interactions of a complex ... function to bridge and gate-keep the full integration, validation, and characterization of ASIC , HW/PCB, SW, FW, and FPGA subsystems in the whole development cycle.… more
    Cadence Design Systems, Inc. (10/08/25)
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  • Sr Principal DFT Application Engineer

    Cadence Design Systems, Inc. (Austin, TX)
    …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate ... is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. + Prior 5-15 years of professional… more
    Cadence Design Systems, Inc. (09/05/25)
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  • Emulation Engineer II

    Microsoft Corporation (Santa Clara, CA)
    …experience. + 2+ years of experience in Application Specific integrated circuit ( ASIC )/ System on Chip (SoC) emulation verification with System Verilog ... software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to… more
    Microsoft Corporation (10/14/25)
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