- Cisco (San Jose, CA)
- …You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a ... a physical design function + Interfaces with vendors and design leads on full chip timing closure, PI, and PV + Owns the full electrical planning and specifications… more
- GE Aerospace (Grand Rapids, MI)
- …by leveraging cutting-edge technology trends and state-of-the-art processor, System On Chip (SoC), and FPGA components. This position is integral to influencing ... digital and analog components. + Maintain expertise in semiconductor processors, System-on- Chip , and FPGA architectures. + Conduct and mentor board-level circuit… more
- Lac Vieux Desert Northern Waters Casino Resort (Watersmeet, MI)
- …Maintains a smooth and efficient game pace; makes accurate and clear chip and cash transactions. Primary Responsibilities: + Provide excellent Guest Service to ... policies and procedures as it relates to this position. + Performs accurate chip and cash transactions. + Receives wagers from customers and pay appropriate game… more
- Micron Technology, Inc. (Folsom, CA)
- …for AI and high-performance computing. In this role, you will lead full- chip floorplanning, top-level synthesis, and layout development for advanced HBM designs, ... on Micron's industry-leading HBM product family. **Responsibilities** + Own full- chip floorplanning, design partitioning, and top-level synthesis with multiple hard… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Protium + Design, integrate, and validate high-speed interface subsystems (SerDes, chip -to- chip links) in full-system emulation environments + Develop end-to-end ... verification flows, including: + System-level modeling (microcontrollers, memories, NoC, controllers, MACs) + Custom test case development and automation + Interface performance analysis and validation + Convert Analog/Mixed-Signal (AMS) parallel and serial… more
- Cisco (San Jose, CA)
- …design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for ... with 6+ years of ASIC or related experience. + Experience with block/full chip SDC development in functional and test modes. + Experience in Static Timing… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …the dynamic and tenacious team solving some of the most complicated challenges in chip power integrity and thermal analysis. We are looking for people that are ... + Excellent knowledge on how power, IR, and EM analyses impact chip planning to IR/EM sign-off. + Fundamental understanding of interconnect modeling, package… more
- Amazon (Austin, TX)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... - Have a "Learn and Be Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale… more
- Broadcom (Irvine, CA)
- …sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology ... facility in California. **Responsibilities** : Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement.… more
- TrustPoint (Dulles, VA)
- …up meetings, and cultivating relationships with key stakeholders in GNSS chip and receiver manufacturing, defense, and critical infrastructure markets. As one ... strategy for commercial GNSS adoption. + Build trusted relationships with GNSS chip and receiver manufacturers; secure LOIs. + Set up meetings, pitch TrustPoint's… more