• Analog/Mixed-signal IC Design Co-Op (June '26-Dec…

    Skyworks (Austin, TX)
    …with frequency and time domain analysis of complex mathematical systems + Familiarity with CMOS layout and layout best practices + Experience with standard ... background, familiarity with schematic capture, architecture definition, circuit implementation, and layout of CMOS analog circuits. Depending on the experience… more
    Skyworks (08/08/25)
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  • Analog/Power IC Design Co-Op (June '26 - Dec '26)

    Skyworks (Austin, TX)
    …frequency and time domain analysis of complex mathematical systems + Familiarity with CMOS layout + Experience with standard electrical engineering lab equipment ... background, familiarity with schematic capture, architecture definition, circuit implementation, and layout of CMOS analog circuits. Depending on experience… more
    Skyworks (08/16/25)
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  • Senior CAD Engineer, Physical Design

    NVIDIA (Santa Clara, CA)
    …5 years industry experience. + Have an in-depth understanding of mosfet device behavior, CMOS layout , and VLSI design. + Experience working with standard cell ... design & layout . + Great interpersonal skills. + A passion for providing excellent support for end-users. NVIDIA offers highly competitive salaries and a… more
    NVIDIA (07/29/25)
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  • Senior CAD Engineer, Custom Circuit Designers

    NVIDIA (Santa Clara, CA)
    …Engineering and 4+ year's experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design + Excellent programming skills + Experience ... with perl, Cadence SKILL, python, tcl + Great communication skills + Passionate about providing excellent support for end-users. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth,… more
    NVIDIA (06/05/25)
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  • CAD Engineer

    NVIDIA (Santa Clara, CA)
    …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Understanding of version control software ... preferably Perforce. + Understanding the regression testing methodology. + Excellent programming skills; experience with perl, python and other scripting languages. + Great interpersonal skills + Passionate about providing excellent support for end-users.… more
    NVIDIA (06/03/25)
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  • Senior ICV CAD Engineer

    NVIDIA (Santa Clara, CA)
    …5+ years of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... perl, Cadence SKILL. + Expertise in ICV in order to support, enhance, and debug foundry DRC and LVS techfiles. + Being able to implement NVIDIA specific DFM, DRC rules using ICV. + Add NVIDIA specific devices in the LVS deck using ICV. + Great interpersonal… more
    NVIDIA (06/03/25)
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  • CMOS Device Integration Engineer, SMTS

    Micron Technology, Inc. (Boise, ID)
    …the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer, you will play a crucial role in the ... development of current and future CMOS technology. You will be responsible for device and...with teams across the organization including Process, Circuit, Design, Layout , Product Engineering, and Modeling/TCAD. Your expertise will be… more
    Micron Technology, Inc. (06/12/25)
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  • Staff Memory CAD Automation Engineer - TPG

    Micron Technology, Inc. (Richardson, TX)
    …verification methodologies, flows, and quality metrics. + 5+ years of experience in CMOS circuit design, layout , and verification. + 5+ years of experience ... and methodologies for next-generation memory designs. Collaborating closely with design, layout , verification, modeling, and process teams, you will be integral in… more
    Micron Technology, Inc. (07/25/25)
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  • Lead Layout Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …and layout design. + Deep understanding of digital and analog circuit layout concepts in submicron CMOS technologies. + Strong background with Cadence custom ... on all the NVIDIA products! What you'll be doing: + Perform physical layout for custom embedded SRAM structures in state-of-the-art sub-micron CMOS technologies… more
    NVIDIA (08/19/25)
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  • Device Engineering Intern, Ulp CMOS (Summer…

    Global Foundries (Malta, NY)
    …you will contribute to the advancement of Ultra Low Power (ULP) CMOS technologies for applications including Automotive, IoT, Aerospace & Defense, and Smart ... roadmap and manufacturing goals. Essential Responsibilities include: + Device test chip layout design + Inline and bench electric test submission and analysis +… more
    Global Foundries (08/14/25)
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