• RFIC Design Engineer (Silicon Engineering)

    SpaceX (Redmond, WA)
    …subsystems and circuits + Develop Analog/Mixed-Signal/RF/microwave circuits in SiGe or CMOS processes + Work with system architects, modem/DSP and ASIC engineers ... functions between hardware and software domains + Perform IC floor planning and layout + Model package and external parasitic components + Evaluate and characterize… more
    SpaceX (01/03/26)
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  • DRAM Product Test Engineer

    Micron Technology, Inc. (Boise, ID)
    …with C/C++ and/or JAVA is required. + Proven understanding of testing for CMOS SoCs. Prefer candidates with outstanding digital, analog, and MXS test programming and ... ATE architecture and test hardware design and debugging, schematic capture, and PCB layout . + ATE test vector conversion tools like VTRAN and proficiency in… more
    Micron Technology, Inc. (01/02/26)
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  • Lead Analog IC Designer

    Cadence Design Systems, Inc. (San Jose, CA)
    …+ Candidate's background should include a minimum of 3 years of experience in CMOS SerDes or high-speed I/O IC design and development + Working knowledge of a ... + Position requires proficiency in using CAD tools for circuit simulation, layout , and physical verification + Cadence tool experience, lab test experience, and… more
    Cadence Design Systems, Inc. (12/05/25)
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  • FPGA Design Engineer

    Applied Materials (Santa Clara, CA)
    …PL. * Implement high-speed IO to realize data transfer between different FPGAs. ** CMOS Sensor & Image Processing** * Integrate and interface camera sensor in FPGA. ... IOs, I2C, UART, SPI. * Work closely with hardware engineers on schematics, layout reviews, and FPGA pin assignment planning. * Support signal integrity, timing, and… more
    Applied Materials (11/27/25)
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  • Principal Analog ASIC Design Engineer

    Ralliant (Beaverton, OR)
    …join our Tektronix design center in Beaverton, Oregon, to help create advanced CMOS , BiCMOS, and HBT RF integrated circuits for our next-generation products. You ... skills. + Willingness to travel domestically if needed. + Experience with layout for critical cells + Familiarity with characterizing designs in laboratory settings… more
    Ralliant (11/25/25)
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  • Scientific Writer

    ThermoFisher Scientific (Pittsburgh, PA)
    …in interacting with internal partners. + Develop scientific copy that conforms to layout and other design parameters while maintaining the consistent voice and style ... and Microsoft Office Suite + Deep knowledge of the Chicago Manual of Style ( CMOS ) and CSE Scientific Style and Format style guides + Ability to perform fact-checking… more
    ThermoFisher Scientific (11/22/25)
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  • Product Yield Enhancement Engineer, HBM

    Micron Technology, Inc. (Boise, ID)
    …PFA and de-processing techniques for failures + In depth understanding of CMOS /FinFET process fabrication levels, steps, and methodologies + Generate organized and ... semiconductor experience in Yield and fault analysis + Computer aided layout and schematic experience + Demonstrated knowledge of semiconductor device physics… more
    Micron Technology, Inc. (11/21/25)
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