- Texas Instruments (Santa Clara, CA)
- …You'll have the opportunity to work in exciting areas such as CPU simulator development, 64-bit vector processor ISA architecture, development and verification etc. ... As a Digital IC Design Engineer, some of your responsibilities may include: + Partner with business teams and system engineering to develop mutually agreeable design specifications + Provide high-level analysis on chip architecture trade-offs to ensure spec… more
- Microsoft Corporation (Hillsboro, OR)
- …(AMBA) protocols; coherency, fabrics, integration of Central Processing Unit ( CPU ) cores, power management, reset, virtualization, interrupts, security, clocking, or ... other complex SOC flows and protocols + Experience with SOC or chip level verification for more than one product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and signing off coverage + Experience… more
- HUB International (Salt Lake City, UT)
- …with Marketing as required to maximize account management results + Collaborate with CPU as required to maximize account management results + Review client insurance ... related contracts as necessary + Prepare management reports as necessary + Acquire understanding of client insurance objectives and critically analyze and compare insurance terms and conditions + Trouble shoot, issue spot, and problem solve matters between the… more
- Fiserv (Omaha, NE)
- …Windows environment. + Perform capacity management and adjust system resources ( CPU , memory, disk) as needed. + Install, uninstall, and troubleshoot third-party ... software programmatically across large server fleets. + Develop automation scripts using PowerShell or Python to streamline operational tasks. + Monitor system health and respond to alerts to ensure maximum uptime. + Utilize tools such as Service Point,… more
- Cadence Design Systems, Inc. (Austin, TX)
- …algorithms, circuit partitioning, graph traversal, circuit detection, multi-threading, memory/ cpu optimization) and be responsible for advancing and creating ... state-of-the-art circuit simulation technologies and solutions. Our ideal candidate must be proficient in C/C++ Unix development. + A thorough knowledge of transistor-level circuit behavior, such as MOSFET/resistor/capacitor, and understanding the custom IC… more
- NVIDIA (Santa Clara, CA)
- …environments would be an asset (eg TRT, ONNX, Triton) + Knowledge of GPU/ CPU architecture and related numerical software Your base salary will be determined based ... on your location, experience, and the pay of employees in similar positions. The base salary range is 148,000 USD - 235,750 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits… more
- NVIDIA (Santa Clara, CA)
- …HPC applications such as LAMMPS, GROMACS, Amber, RTM, etc + Experience with GPU/ CPU benchmarking on cloud solutions from AWS, GCP, Azure + GPU programming experience ... in CUDA, OpenACC, or OpenCL + Familiarity with software compilers such as GNU, Intel Composer, or PGI + Previous experience with computer clusters, Slurm, Kubernetes. We have some of the most forward thinking and hardworking people in the world working for us… more
- Bank of America (Newark, DE)
- …platform stability, resilience, and performance. Ensure non-functional requirements for performance ( CPU usage, latency). + **** MS in Computer Science or related ... field **Skills:** + Analytical Thinking + Architecture + Result Orientation + Solution Design + Technical Strategy Development + Application Development + Collaboration + Data Management + DevOps Practices + Risk Management + Agile Practices + Automation +… more
- Oracle (Hartford, CT)
- …performant code at a low level (eg, C, raw sockets, CPU /vector instructions, memory/cache optimization). Familiarity with high-performance IO paths; understanding of ... cross-region networking and latency trade-offs. BS/MS in Computer Science, Electrical/Computer Engineering, or equivalent practical experience; proven technical leadership and mentoring. Preferred: Expertise in virtualization/containers. Java performance… more
- Snap Inc. (Santa Monica, CA)
- …robust failover, replication, and cluster topology management and optimize cpu performance, memory usage, persistence, and eviction strategies for low-latency ... workloads. + Enhance observability: metrics, tracing, and debugging tools for cache infra. + Drive benchmarking, tuning, and capacity planning for 125M+ QPS scale. + Evaluate the technical tradeoffs of major decisions and be a strong technical mentor +… more