• Senior CPU Architecture and Performance…

    Google (Portland, OR)
    …performance and design. + Experience in high-performance CPU architecture and CPU blocks. + Experience in performance modeling, analysis , correlation, and ... phases. You will be planning a project and guiding CPU architects and working with engineers in power...both architecture and performance angles. + Define and write CPU subsystem architecture specifications. + Lead the… more
    Google (11/07/25)
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  • Systems Engineer, Power Design SME

    Celestica (San Jose, CA)
    …optical, switch, memory, NPU, CPU , GPU components + Failure mode analysis + Good understanding of power efficiency optimization schemes + Experience ... contribute or lead the specification, design, and debug of complex power delivery systems for datacenter products. **Skills & Responsibilities:** + Engage with… more
    Celestica (11/29/25)
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  • Senior Lead Storage & Server Test Engineer…

    Celestica (Merrimack, NH)
    …and NAS. * Strong understanding of server architectures (x86, ARM, GPU servers), CPU /memory subsystems, PCIe, and power management. * Strong understanding of ... server architectures (x86, ARM, GPU servers), CPU /memory subsystems, PCIe, power management, and Baseband Management Controllers (BMC) functionality. *… more
    Celestica (10/14/25)
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  • Manufacturing Test Lead

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a Manufacturing Test Lead to join our team. Join us in this exciting AI revolution. Be part of ... changing mission. \#azurehwjobs #HIFE #AHSI #CHIE **Responsibilities** + Define and lead end-to-end manufacturing test strategies for PCBAs, storage enclosures, and… more
    Microsoft Corporation (12/03/25)
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  • Senior Lead Storage & Server Test Engineer…

    Celestica (Merrimack, NH)
    …and NAS. * Strong understanding of server architectures (x86, ARM, GPU servers), CPU /memory subsystems, PCIe, and power management. * Strong understanding of ... server architectures (x86, ARM, GPU servers), CPU /memory subsystems, PCIe, power management, and Baseband Management Controllers (BMC) functionality. *… more
    Celestica (10/14/25)
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  • Camera Use Case Tech Lead , Silicon

    Google (San Diego, CA)
    …Video, Display and Audio) power optimizations. + Experience with Mempath and CPU workload analysis and power optimizations. + Experience with software ... performance goals for mobile SoCs. + Experience with SoC power modeling and analysis . + Experience with...lead a high-functioning global team to deliver camera power . Information collected and processed as part of your… more
    Google (11/20/25)
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  • Senior Silicon and System Product Lead

    NVIDIA (Santa Clara, CA)
    …and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: + Drive ... We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation...datacenter is preferred. + Deep understand of critical path analysis , power /performance analysis , process technologies,… more
    NVIDIA (10/24/25)
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  • Hardware Security, Lead Engineer

    Oracle (Santa Clara, CA)
    …with hardware level diagnostics and debugging, including early stage bring-up and power -on, platform firmware debugging, CPU complex/memory complex debugging and ... for both peer customer organizations and the wider hardware organization + Lead key hardware-focused security projects in conjunction with Oracle firmware and Oracle… more
    Oracle (11/25/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …Static Timing Analysis ) + Debug and resolve complicated PPA, Low Power implementation and TAT issues. + Exceptional troubleshooting and analytical skills + ... an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE...(LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design services projects… more
    Cadence Design Systems, Inc. (12/03/25)
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  • Lead Speed and Reliability Engineer - DFP

    NVIDIA (Santa Clara, CA)
    …stand out from the crowd: + Familiarity with statistical methods and tools for data analysis + Background with substrate and power supply noise analysis and ... DFP team is looking for a Speed and Reliability Lead . You will be leading and crafting testability features...test chips) fabricated using innovative processes for speed, performance, power , yield and quality. + Provide guidance to silicon… more
    NVIDIA (11/15/25)
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