• Senior Mechanical Engineer

    Actalent (Valencia, CA)
    …designs from early concepts, focusing on Design for Manufacturability (DfM) and Design for Test ( DfT ) concerns. This role requires participating in ... Job Title: Senior Mechanical Engineer Job Description As a Sr Mechanical ...for various stakeholders. + Experience in transferring products from design to manufacturing. + Demonstration of DfT more
    Actalent (10/11/25)
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  • Lead ASIC Design Engineer , Kuiper…

    Amazon (Austin, TX)
    …logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform initial synthesis ... refugee or granted asylum. Key job responsibilities Key job responsibilities RTL Design and development of custom blocks. Integration of large subsystems Gate Level… more
    Amazon (09/26/25)
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  • ASIC Design Engineer , Kuiper ASIC…

    Amazon (Austin, TX)
    …logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform initial synthesis ... Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation… more
    Amazon (09/10/25)
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  • ASIC Design Engineer , Kuiper ASIC…

    Amazon (Austin, TX)
    …logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform initial synthesis ... Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation… more
    Amazon (08/30/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …analysis of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design -for- test ( DFT ) and logic design is a plus. + ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...Work as part of a global circuits team to design the state of the art in silicon monitors… more
    NVIDIA (10/11/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, ... and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring… more
    Amazon (09/17/25)
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  • Principal Digital Design Engineer

    Cadence Design Systems, Inc. (Cary, NC)
    … implementation + Embedded uC Designs + Synthesis and SDC Creation + Scripting of design automation + Debugging verification test cases / SVA's to cover the ... quality. The candidate will contribute to digital architecture, digital RTL, low power design , synthesis and timing analysis, and behavioral coding for all IPs in… more
    Cadence Design Systems, Inc. (09/11/25)
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  • Memory Circuit Design Engineer

    Broadcom (Mendota Heights, MN)
    …before you apply.** **Job Description:** We are looking for energetic and passionate memory design engineers to join our Central Engineering Group and be part of an ... Job Responsibilities** + Analyze different memory architectures and highlight the tradeoffs + Design and build memory or circuit blocks at the gate or transistor… more
    Broadcom (09/12/25)
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  • High Speed RTL Design Engineer

    Broadcom (San Jose, CA)
    …tools such as NCVerilog, NCSIM, Simvision, Lint.** + **Exposure to Design for test , understanding of scan concept and writing DFT friendly RTL.** + **Deep ... of experience in high speed ADC based SerDes RTL design .** + **Proficient with Verilog-HDL/System Verilog coding for PAM4...interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as… more
    Broadcom (08/16/25)
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  • Senior ASIC Design Engineer

    Amazon (San Diego, CA)
    …right silicon solutions, and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block . Work with the ... verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C...C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with… more
    Amazon (10/08/25)
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