- NVIDIA (Santa Clara, CA)
- …involves working with other IP architects, designers, verification, Physical Design, Software, DFT , Security, Automotive Safety and others. You will be required to ... capture these requirements in various architecture documents clearly and drive their reviews. You will be required to develop and improve architectural C-models and support the teams that use them. You will also be required to review both upstream and… more
- NVIDIA (Austin, TX)
- …experience in object-oriented programming + Prior design on system level IP (Clocks/ DFT /Resets) + Experience developing methodologies used by others + Hands- on ... silicon debug is a plus. + Exposure to physical design With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant people in the world… more
- Teledyne (Goleta, CA)
- …constraints (timing, area, power). + Multi-corner, multi-mode (MCMM) analysis. + DFT /ATPG insertion (scan chains, BIST for ASIC testability). + Clock/Power ... optimization for low-power ASICs. + Perform Back-End Physical Design as needed + Floorplanning and power grid design. + Place and Route (APR) with congestion management. + Timing closure across PVT corners. + DRC, LVS, extraction and signoff. + Perform RTL… more
- Micron Technology, Inc. (Folsom, CA)
- …communication skills. **Preferred Qualifications** + Experience with UPF, power analysis, DFT /scan insertion, ATPG, and timing model generation. + Proficiency in ... scripting languages like Python and Perl. + Familiarity with advanced automatic place-and-route tools. The US base salary range that Micron Technology estimates it could pay for this full-time position is: $146,000.00 - $247,000.00 Our salary ranges are… more
- Broadcom (Fort Collins, CO)
- …with multiple cross functional teams--analog design, digital design, physical composition, DFT , timing, and customers--to build PHYs + Work with physical composition ... teams and interposer design teams + Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs + Work with teams to analyze power integrity (droop, EM, etc ) in various use cases and workloads +… more
- NVIDIA (Hillsboro, OR)
- …and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing: + Define and develop ... system-level methodologies and tools to build SOCs in an efficient and scalable manner + Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them + Own front-end design quality checks… more
- NVIDIA (Santa Clara, CA)
- …a deep understanding of ASIC design flow including RTL design and verification, DFT , and ECO. + Strong communication and interpersonal skills are required along with ... the ability to work in a dynamic, global team. NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do… more
- Amazon (Cupertino, CA)
- …responsibilities - integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of the ASIC design ... team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications. - Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.… more
- Broadcom (San Jose, CA)
- …LVS/DRC - Low power, signal integrity experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good ... debug skill and be able to work around issues - Tape out experience - must be a good team player **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $120,000 - $192,000 This position is also eligible… more
- Cisco (San Jose, CA)
- …member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. + Option to also do ... block level RTL design or block or top-level IP integration. + Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level. + Helping develop and apply methodology to ensure correctness… more