- Amazon (Sunnyvale, CA)
- …-Master's or Ph.D degree in Electrical / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an ... time to revenue. Innovators will be delighted with our integrated verification /validation environment that is used to perform architectural modeling to post-silicon… more
- Cisco (Maynard, MA)
- …Cadence Innovus or Synopsys ICC2 * Synthesis experience including Synopsys DC/FC * Formal Verification experience using tools such Synopsys Formality or Cadence ... floor planning & partitioning, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR,… more
- Broadcom (Fort Collins, CO)
- …RTL design to synthesis, RTL/ netlist audits (using tools such as Spyglass), Formal verification , constraints development and analysis w/ emphasis on CDCs in ... Design: SerDes Digital IP Design Engineer:** Oversees definition, design, verification co-definition, and documentation for SerDes development. Performs architecture… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Must have a deep te c hni c al knowledge and understanding of digital verification flows, including simulation, debug, coverage, formal , and Verification IP. ... the c ore te c hnology requirements in digital verification , leadership for defining and c oordinating disruptive te...Developing and leading pre/post-sales c ampaigns to grow digital verification software adoption in assigned global acc ount. +… more
- Broadcom (Broomfield, CO)
- …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). + Drive tools and methodologies to achieve desired PPA… more
- Renesas (Duluth, GA)
- …timing analysis and creation of place and route constraints + Proficiency in formal verification , linting, and CDC/RDC checking + Knowledge of asynchronous clock ... and high-speed design concepts + Participate in design, architecture, and verification reviews + Oversee digital backend design, including synthesis, static timing… more
- Google (Sunnyvale, CA)
- …and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or fullchip. + Work with ... (QoR). + Experience in sign-off closure techniques, including SSTA, physical verification , EMIR, and low-power implementation (UPF/CPF). + Experience in integrating… more
- Northrop Grumman (Los Angeles, CA)
- …etc. + Generation of complex test benches in Modelsim or Questasim to support formal Verification . + Familiarity with the VxWorks RTOS, its architecture and ... Technology, Engineering or Mathematics) discipline with 12 years of digital verification engineering experience using industry standard simulation tools; 10 years… more
- Northrop Grumman (Huntsville, AL)
- …execution, reporting, and integration support. * Prepare detailed test reports and support formal verification of the system. * Compile data and define changes ... * Interface with software developers and systems engineers in support of verification . * Product integration, regression, and verification testing including… more
- Broadcom (Broomfield, CO)
- …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able to drive tools and methodologies to… more