- Microsoft Corporation (Mountain View, CA)
- …involving complex NOC. + Working knowledge of writing assertions, coverage and / or formal verification . + Knowledge of industry standard bus interfaces such as ... to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer for customer focused solutions, insight and industry knowledge to envision… more
- Cisco (Maynard, MA)
- …Experience with C++ templates . Lab silicon validation experience . Experience with Formal Verification methodologies and tools such as Jasper or VCFormal **Why ... empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent… more
- Lockheed Martin (Highlands Ranch, CO)
- …multiple verification strategies as appropriate, including UVM/SystemVerilog, emulation, formal verification and lab based techniques\. * Experience ... **Description:** Join Our Team as a **ASIC/FPGA Verification Engineer** where you will work on the...Space's Silicon Solutions team and seeking a future\-looking Principal Verification Engineer who is able to case and realize… more
- NVIDIA (Santa Clara, CA)
- …+ Expertise in industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage metrics, profiling tools, ... The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks Team is… more
- NVIDIA (Santa Clara, CA)
- … verification of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other verification flows. ... We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes require… more
- US Tech Solutions (Goleta, CA)
- …such as Linux and Android would be a plus. + Experience in assertions and formal verification is preferred. + Experience in JTAG is preferred. + Experience in ... **Job Description:** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI,… more
- Broadcom (San Jose, CA)
- …and driving verification closure * Hands on experience in CDC check, formal verification , functional coverage, gate level debug and emulation tools * Very ... custom AI chips. This position is responsible for IP and subsystem verification , including SerDes and processor subsystem among many other IPs. **Requirements:** *… more
- Cisco (San Jose, CA)
- …+ Understanding of networking and packet forwarding architectures highly desirable + Knowledge of formal verification tools (eg, Jasper or VC Formal ) + ... team can provide. **Your Impact** As an ASIC Design Verification Engineer, you will play a critical role in...create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with… more
- Cisco (Maynard, MA)
- …modulation techniques such as QAM + Lab silicon validation experience + Knowledge of Formal Verification methodologies and tools such as Jasper + Ability to work ... culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Intern Engineer will be a member of a team working on next generation… more
- Amazon (Austin, TX)
- …C, C or Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an ... you will: . Implement a state of the art verification environment to facilitate testing of the RTL against...and communication systems team and participate in system level verification using test benches constructed using UVM . Develop… more
Recent Jobs
-
Principal Information Manager
- Parsons Corporation (Washington, DC)
-
Senior Production Test Engineer (Missile Assembly)(ATE)
- Lockheed Martin (Troy, AL)