• ASIC Verification Engineer - Acacia…

    Cisco (Maynard, MA)
    …Experience with C++ templates . Lab silicon validation experience . Experience with Formal Verification methodologies and tools such as Jasper or VCFormal **Why ... empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent… more
    Cisco (12/20/25)
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  • Custom SOC IP Verification Engineer

    NVIDIA (Santa Clara, CA)
    …or model integration. Ways to stand out from the crowd: + Experience with formal verification or assertion-based verification (SVA). + Knowledge of RISC-V ... NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC...to be. This role specifically requires a skilled ASIC Verification Engineer with expertise in cache coherency protocols and… more
    NVIDIA (12/19/25)
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  • Senior SOC Fabric Verification Engineer

    Microsoft Corporation (Hillsboro, OR)
    …benches, checkers and stimulus using C, System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), and/or Formal Verification + Aptitude for ... and we are looking for a **Senior SOC Fabric Verification Engineer** to help achieve that mission. The Compute...hardware. We are looking for a **Senior SOC Fabric Verification Engineer** with a dedicated passion for customer focused… more
    Microsoft Corporation (12/12/25)
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  • ASIC/FPGA Principal Verification Engineer…

    Lockheed Martin (Highlands Ranch, CO)
    …multiple verification strategies as appropriate, including UVM/SystemVerilog, emulation, formal verification and lab based techniques\. * Experience ... **Description:** Join Our Team as a **ASIC/FPGA Verification Engineer** where you will work on the...Space's Silicon Solutions team and seeking a future\-looking Principal Verification Engineer who is able to case and realize… more
    Lockheed Martin (12/06/25)
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  • Sr. ASIC Design Verification Engineer…

    Amazon (San Diego, CA)
    …. Participate in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
    Amazon (12/13/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    …+ Expertise in industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage metrics, profiling tools, ... The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks Team is… more
    NVIDIA (12/10/25)
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  • Senior Circuit Verification Engineer

    NVIDIA (Santa Clara, CA)
    verification of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other verification flows. ... We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes require… more
    NVIDIA (12/09/25)
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  • SOC Design Verification Lead / Manager

    Capgemini (Santa Clara, CA)
    …(Python, TCL). + Strong grasp of **functional coverage** , simulation, emulation, and formal verification . + Proven ability to **lead teams** , **influence ... **Architect and Implement Solutions** Design and deploy **end-to-end SoC verification environments** leveraging UVM, UPF, and advanced methodologies. **Engineer… more
    Capgemini (12/05/25)
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  • UVM/ SystemVerilog Design Verification

    US Tech Solutions (Goleta, CA)
    …such as Linux and Android would be a plus. + Experience in assertions and formal verification is preferred. + Experience in JTAG is preferred. + Experience in ... **Job Description:** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI,… more
    US Tech Solutions (11/08/25)
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  • Verification Engineer

    Broadcom (San Jose, CA)
    …and driving verification closure * Hands on experience in CDC check, formal verification , functional coverage, gate level debug and emulation tools * Very ... custom AI chips. This position is responsible for IP and subsystem verification , including SerDes and processor subsystem among many other IPs. **Requirements:** *… more
    Broadcom (10/30/25)
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