- Microsoft Corporation (Raleigh, NC)
- …manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** + Establish yourself ... environments in industry standard languages like SVTB UVM or formal verification . + 3+ years of experience writing scripts/software with industry standard… more
- Microsoft Corporation (Raleigh, NC)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Principal Verification Engineer ** to join the team. **Responsibilities** + Lead an SoC ... environments in industry standard languages like SVTB UVM or formal verification . + 2+ years of pre-silicon verification technical leadership,… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test plan 3. Drive… more
- Meta (Sunnyvale, CA)
- …transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC ... verification plans, build verification test benches to enable IP/sub-system/SoC level ...or more of the following areas: SystemVerilog Assertions (SVA), Formal , and Emulation 15. Prior working knowledge of Audio/image/Video… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks Team ... in industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage metrics, profiling tools, X prop, etc.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes ... verification of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other verification flows. +… more
- US Tech Solutions (Goleta, CA)
- …internal components and send data. **Responsibilities** + As a UVM/ SystemVerilog Design Verification Engineer , you will own functional verification for a ... as Linux and Android would be a plus. + Experience in assertions and formal verification is preferred. + Experience in JTAG is preferred. + Experience in analog… more
- Draper (Boston, MA)
- …Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs ... will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... work + Experience with PCIe subsystems + Experience with the use of formal verification methods + Experience in RTL design for FPGA or emulation + Experience… more