- Capgemini (Santa Clara, CA)
- …(Python, TCL). + Strong grasp of **functional coverage** , simulation, emulation, and formal verification . + Proven ability to **lead teams** , **influence ... Lead Products & Systems Engineer At Capgemini Engineering, the world leader in...verification environments** leveraging UVM, UPF, and advanced methodologies. ** Engineer tailored solutions** that align with client objectives and… more
- Northrop Grumman (Jessup, MD)
- …generate manufacturing test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification , and static timing. Knowledge of scan insertion and ... the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom...Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification , and static timing using state-of-the-art… more
- PPL Corporation (Louisville, KY)
- …operating policies and standards compliance. Position to be filled at the Engineer I, II, III, or Principal level based upon applicant's qualifications and ... timely installation of field equipment, AMI network optimization, system security verification and any relevant system upgrade analysis. + Directs and/or supports… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year Design … more
- City and County of San Francisco (San Francisco, CA)
- …application. Under the general direction of the Train Control Upgrade Project Lead Engineer , the Senior Signaling Engineer leads the signaling design section of ... the SFMTA owner's engineering team. The Senior Signaling Engineer assists the Train Control Upgrade Project Lead Engineer with oversight duties related to… more
- Lockheed Martin (Denver, CO)
- …to reduce total system cost and schedule\. * Partner with a Principal Verification Engineer to architect cohesive approaches to SoC development that reduce ... modern ASIC/FPGA/SoC verification strategies as appropriate, including UVM/SystemVerilog, emulation, formal verification and lab based techniques a plus\. *… more
- RTX Corporation (Tucson, AZ)
- …and Test Capabilities (SE&TC) organization is currently hiring a **Principal Systems Engineer , Responsible Systems Engineer (RSE) - Cameo** to join our ... multi-disciplines to shape innovative solutions for our customers. The Principal Systems Engineer is a technical role contributing directly to the architecture and… more
- Northrop Grumman (Melbourne, FL)
- …confirmation.** **Northrop Grumman Aeronautics Systems** sector is seeking a **Responsible Engineer or Principal Responsible Engineer ** **- Fuel Systems** with ... work available. **Key responsibilities may include:** + Performing responsible engineer activities, which include all aspects of fuel subsystem/component design… more
- RTX Corporation (Melbourne, FL)
- …. + Must possess at least 5 years of experience as a system verification engineer , including developing verification test plans, test cases and ... Rockwell Collins Inc. d/b/a Collins Aerospace has an opening for a Principal Engineer , Systems Engineering in Melbourne, FL. International travel to India two times… more
- Eliassen Group (San Diego, CA)
- **Senior Software Test Engineer ** **San Diego, CA** **Type:** Contract **Category:** Quality Assurance (QA) **Industry:** Life Sciences **Reference ID:** JN ... a leader in biotechnology, has an excellent opportunity for an Senior Software Test Engineer to work on a 6-month contract opportunity. Work will be a hybrid… more