• Design Verification Engineer

    Arrow Electronics (Mountain View, CA)
    **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... functional and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification more
    Arrow Electronics (09/25/25)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips...test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification more
    Meta (11/08/25)
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  • Senior Circuit Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes ... of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other...products. + Engaging with industry tool AEs to qualify new tool releases, learn about new tool… more
    NVIDIA (12/09/25)
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  • Sr FPGA Engineer - Verification

    Medtronic (Lafayette, CO)
    … Verify FPGA systems and components using constrained random methodologies including UVM and Formal Verification Collect and refine FPGA and SOC verification ... in our technical functions to advance existing technology or introduce new technology and therapies. Formulates, delivers and/or manages projects assigned and… more
    Medtronic (12/13/25)
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  • Senior UVM Digital Verification

    Draper (Boston, MA)
    …Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs ... problem domains, with ability to quickly become knowledgeable in new domains. * Identify and develop relevant modeling and...will develop verification approaches, author and execute verification plans, and use formal analysis tools.… more
    Draper (10/11/25)
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  • Systems Integration & Verification

    Lockheed Martin (Boulder, CO)
    …any other are with Lockheed Martin Space** **OVERVIEW:** At the dawn of a new space age, Lockheed Martin is a pioneer, partner, innovator and builder\. Our amazing ... develop your career as a Systems Integration and Test Engineer ? Do you want to be part of a...to ensure completeness of test program * Independently author formal test procedures, standard operating procedures, and data reports… more
    Lockheed Martin (11/26/25)
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  • Design Verification Engineer

    Amazon (Austin, TX)
    …Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - ... solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our… more
    Amazon (10/02/25)
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  • MLA IP Design Verification Engineer

    Amazon (Cupertino, CA)
    …Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - ... around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our...& Career Growth Our team is dedicated to supporting new members. We have a broad mix of experience… more
    Amazon (11/27/25)
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  • Principal/ Senior Principal Digital ASIC Circuit…

    Northrop Grumman (Jessup, MD)
    …generate manufacturing test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification , and static timing. Knowledge of scan insertion and ... the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom...Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification , and static timing using state-of-the-art… more
    Northrop Grumman (12/05/25)
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  • Engineer I, II, III, or Principal - Meter…

    PPL Corporation (Louisville, KY)
    …operating policies and standards compliance. Position to be filled at the Engineer I, II, III, or Principal level based upon applicant's qualifications and ... timely installation of field equipment, AMI network optimization, system security verification and any relevant system upgrade analysis. + Directs and/or supports… more
    PPL Corporation (12/06/25)
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