- Amazon (Sunnyvale, CA)
- …and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA… more
- Lockheed Martin (Denver, CO)
- … team in the world, and are seeking a highly talented and motivated **ASIC & FPGA Verification Engineer ** who has a passion for microchip design and space\. ... **Description:** Join Our Team as an **ASIC & FPGA Lead Verification Engineer **...for a given design\. * Use SystemVerilog and Universal Verification Methodology \( UVM \) to verify a design… more
- BAE Systems (Westminster, CO)
- …incentives may be available based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR** ... used across multiple projects. + Work in a System Verilog/ UVM environment developing tests, testbenches, UVM components,...regressions/testlists. + Be responsible for generating and executing the FPGA Verification Test Plan and FPGA… more
- The Boeing Company (Mountain View, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/ FPGA Engineer on the Boeing Electronic Products team you will develop ... Intelligence & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to… more
- Northrop Grumman (Annapolis Junction, MD)
- …+ Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl, Python, ... for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a... FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting… more
- BAE Systems (Westminster, CO)
- …development environment to provide continuously evolving capabilities in space payloads. As an FPGA Verification engineer , you will work with a team ... including Xilinx Vivado/Vitis and Mentor Modelsim/Questasim. + Experience with OVM/ UVM Verification methodologies. + Ability to work...based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K… more
- BAE Systems (San Diego, CA)
- …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117193BR** EEO ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa… more
- Lockheed Martin (Orlando, FL)
- **Description:** You will be a FPGA Design & Verification Lead at Lockheed Martin, responsible for designing, simulating, and integrating Field\-Programmable ... cutting\-edge technologies\. **What You Will Be Doing** As a FPGA Design & Verification Lead, you will...* Utilizing prior experience with Microchip FPGAs, Xilinx FPGAs, UVM , and GitLab to support FPGA design… more
- Lockheed Martin (Fort Worth, TX)
- …Works IRADs\. With the teams unique expertise in System Verilog and the Universal Verification Methodology \( UVM \) in verifying FPGA \-based designs on Linux, ... are** _Lockheed Martin_ You will be a ASIC & FPGA Design Engineer on the Microelectronics Development...Secret security clearance **Desired Skills:** * Experience with modern verification methodologies such as UVM , OVM or… more
- RTX Corporation (Tucson, AZ)
- …the world, from the ground to exoatmospheric environments and into space. As a **Senior FPGA Design Engineer ** you will develop FPGA designs for all major ... FPGA /ASIC design (VHDL and/or Verilog coding) or FPGA /ASIC verification (SystemVerilog coding) + Xilinx or...serial interfaces and multi-gigabit transceivers (MGTs) + Constrained random verification in UVM using System Verilog +… more