• Fpga Design Engineer

    Actalent (Herndon, VA)
    …Clearance* Job Description We are seeking a FPGA /ASIC Design Engineer responsible for the architecture, implementation, and verification /validation through ... and/or ASICs. + Write and debug tests/sequences for end-to-end simulation using the UVM framework with System Verilog Assertions. + Conduct SW driven validation on… more
    Actalent (10/16/25)
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  • FPGA Design Engineer II

    BAE Systems (Westminster, CO)
    …digital electronics, FPGAs, and embedded processor systems. + Experience with OVM/ UVM Verification methodologies. + Experience developing specifications, cost, ... may be available based on position level and/or job specifics. ** FPGA Design Engineer II** **111253BR** EEO Career Site Equal Opportunity Employer. Minorities .… more
    BAE Systems (10/16/25)
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  • Senior FPGA Development Engineer

    Amazon (Arlington, VA)
    …Web Services (AWS) connectivity and is looking for help. AWS seeks a Senior FPGA Development Engineer with experience developing programmable logic on the most ... Electrical Engineering or a related field - Knowledge of UVM and Matlab - Experience in communication theory, OFDM,...power, area analysis and trade-offs - Experience with modern ASIC/ FPGA design and verification tools - Experience… more
    Amazon (10/10/25)
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  • Senior FPGA Design Engineer

    GE Aerospace (Bohemia, NY)
    …sustainable flight and believe in our talented people to make it happen. The Senior FPGA Design Engineer will play a critical role in designing, developing, and ... into cutting-edge aerospace products. Your expertise in digital design, verification , and FPGA /ASIC development will contribute to...Libero and Xillinx Vivado. + Experience in VHDL and UVM Test Benches. + Experience with the Mentor Graphics… more
    GE Aerospace (10/08/25)
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  • Principal Digital Verification

    Northrop Grumman (Linthicum Heights, MD)
    …DoD secret clearance and Special Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM + Experience developing testplans, ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM more
    Northrop Grumman (10/03/25)
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  • Senior Design Verification Engineer

    Amazon (Sunnyvale, CA)
    UVM , assertions and coverage driven verification . Experience using multiple verification platforms: UVM test bench, FPGA , emulator, software ... of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on...with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write… more
    Amazon (09/04/25)
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  • Staff Lead Design Verification

    Northrop Grumman (Annapolis Junction, MD)
    …culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will ... in gate timing requirements + Develop comprehensive Universal Verification Methodology ( UVM ) simulation environments **Collaborative Processes:** + Work… more
    Northrop Grumman (10/16/25)
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  • Senior ASIC Verification Engineer

    Tarana Wireless (Milpitas, CA)
    …will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate to solve ... generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification...+ BSEE required/MSEE preferred + 5-12 years of related Verification experience + Strong knowledge of UVM more
    Tarana Wireless (09/25/25)
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  • Staff Digital Verification Engineer

    Northrop Grumman (Annapolis Junction, MD)
    …work will be done 100% onsite in Linthicum, MD._** **Basic Qualifications Staff Digital Verification Engineer :** + Bachelor's degree in a technical area (BSEE or ... able to obtain and maintain a security clearance.** **Preferred Qualifications Staff Digital Verification Engineer :** + Advanced Degree either MS or PhD +… more
    Northrop Grumman (08/27/25)
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  • Senior Digital Verification Engineer

    Huntington Ingalls Industries (Fort Meade, MD)
    …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
    Huntington Ingalls Industries (10/09/25)
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