- BAE Systems (Westminster, CO)
- …digital electronics, FPGAs, and embedded processor systems. + Experience with OVM/ UVM Verification methodologies. + Experience developing specifications, cost, ... may be available based on position level and/or job specifics. ** FPGA Design Engineer II** **111253BR** EEO Career Site Equal Opportunity Employer. Minorities .… more
- Northrop Grumman (Linthicum Heights, MD)
- …DoD secret clearance and Special Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM + Experience developing testplans, ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM… more
- Data Device Corporation (Bohemia, NY)
- …language & Verification Frameworks: Expertise inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: ... Senior Engineer ( Verification Engineer ) Department:Software...field). + Experience: 8-15 years of hands-on experience in FPGA verification and development of complex digital… more
- Northrop Grumman (Jessup, MD)
- …culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will ... in gate timing requirements + Develop comprehensive Universal Verification Methodology ( UVM ) simulation environments **Collaborative Processes:** + Work… more
- Broadcom (San Jose, CA)
- …verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM ); designing verification ... flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM , etc.), C/C++, Perl, and scripting skills. +… more
- Northrop Grumman (Jessup, MD)
- …work will be done 100% onsite in Linthicum, MD._** **Basic Qualifications Staff Digital Verification Engineer :** + Bachelor's degree in a technical area (BSEE or ... able to obtain and maintain a security clearance.** **Preferred Qualifications Staff Digital Verification Engineer :** + Advanced Degree either MS or PhD +… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
- Amazon (North Reading, MA)
- … verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - Strong ... silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a...Build assertions, traffic generators and scoreboards in SystemVerilog and UVM - Execute testplans and perform rigorous debug Basic… more
- Cisco (Maynard, MA)
- …company culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Intern Engineer will be a member of a team working on ... highly-complex ASICs that are used in these next-generation telecom systems. The engineer in this role uses sophisticated verification techniques to complete… more
- Renesas (Austin, TX)
- Senior Firmware Verification Engineer Job Description Renesas Electronics America is seeking a mid-level PMIC Firmware Verification Engineer to join our ... Effective written and verbal communication. **Preferred Qualifications** + Experience with UVM or other structured verification methodologies. + Familiarity with… more