- Tarana Wireless (Milpitas, CA)
- …will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate to solve ... generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification...+ BSEE required/MSEE preferred + 5-12 years of related Verification experience + Strong knowledge of UVM … more
- Northrop Grumman (Annapolis Junction, MD)
- …work will be done 100% onsite in Linthicum, MD._** **Basic Qualifications Staff Digital Verification Engineer :** + Bachelor's degree in a technical area (BSEE or ... able to obtain and maintain a security clearance.** **Preferred Qualifications Staff Digital Verification Engineer :** + Advanced Degree either MS or PhD +… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
- Huntington Ingalls Industries (Roanoke, VA)
- …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Active Secret… more
- Amazon (North Reading, MA)
- … verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - Strong ... silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a...Build assertions, traffic generators and scoreboards in SystemVerilog and UVM - Execute testplans and perform rigorous debug Basic… more
- Amazon (San Diego, CA)
- …program . Write tests in C/C++ to execute on embedded CPU . Develop tests for FPGA and emulation platforms . Run formal verification of complex blocks to ensure ... and communication systems team and participate in system level verification using test benches constructed using UVM ,...level verification using test benches constructed using UVM , System C and DPI-C . Develop a highly… more
- Renesas (Austin, TX)
- Sr Staff Design Verification Engineer Job Description * Plan the verification of complex SoC & design blocks by fully understanding the design specification ... environments using System Verilog. * Create and support UVM compliant test-bench architecture * Formally verify designs with...embedded MC Company Description Renesas is seeking a SoC/IP Verification Engineer for our Infrastructure Power team… more
- Google (Mountain View, CA)
- ASIC Design Verification Engineer , Devices and Services _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving ... performance, efficiency, and integration. As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer , you will be part of a Research and… more
- Google (Mountain View, CA)
- Staff ASIC Design Verification Engineer , Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes and ... at RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology ( UVM ). + Experience with system-level architecture, scripting languages,… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we ... which you will verify. + Work with and enable FPGA and software teams to ensure that software is...like Debussy, GDB). + Background with System Verilog and UVM based methodology for ASIC verification . Ways… more