- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask ... Have a BSEE or equivalent experience with Minimum of 6+ proven experience in Mask and Layout Design . + Deep understanding of analog circuit layout … more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a ... a BSEE or equivalent experience. + Minimum of 7+ years industry experience in Mask and Layout Design . + Deep understanding of analog circuit layout … more
- MIT Lincoln Laboratory (Lexington, MA)
- …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... radiation-hard CMOS, and other emerging integrated circuit technologies. The engineer will work in the Cadence environment, with which...in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Mask Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... hardworking, creative, and highly motivated engineers to work on the physical layout design and development of our next generation custom SRAM macro-IPs. As part… more
- Capgemini (Minneapolis, MN)
- …find the fastest way to complete layout * Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent ... **About the job you're considering** * 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent… more
- MIT Lincoln Laboratory (Lexington, MA)
- …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... engineer will collaborate with others involved in mask layout from basic layout ...o Programming in Perl, TCL, or Python o RF layout design experience o Experience with Cadence… more
- Texas Instruments (Dallas, TX)
- …28nm, and 20nm processing nodes; FEOL integration a plus + Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout ... **Change the world. Love your job.** A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices… more
- Google (Goleta, CA)
- …integration. As a Quantum Integrated Circuit Designer, you will support the physical design of quantum processors and associated analog, DC, and RF devices and help ... to mainstream our interface infrastructures between design and other teams. Our Quantum Processor designs are...an iterative process of working with custom programmatic CAD layout tools, graphical layout tools such as… more
- Global Foundries (Malta, NY)
- …www.gf.com . Summary of Role: GlobalFoundries Fab8 is seeking a motivated R&D design enablement engineer to become part of our state-of-the-art 300mm fabrication ... design rules , library device ( TSV) layouts, layout vs schematic( LVS) requirements , device model terminals....vehicle content specifications and the associated tapeout process (including mask reviews ). + Develop expertise in drafting test… more
- Texas Instruments (Dallas, TX)
- …role requires a strong understanding of lithography, RET (Resolution Enhancement Technology), layout design , and process integration. You will collaborate with ... environment. + Excellent problem-solving, analytical, and communication skills. + Familiarity with layout design tools (eg, Cadence Virtuoso). + Knowledge of … more