- NVIDIA (Santa Clara, CA)
- …human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior ... Mask Layout Design Engineer ! Someone who is excited to join a growing and multifaceted group of diverse individuals responsible for handling significant… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing ... BSEE or equivalent experience. + Minimum of 7+ years industry experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in… more
- MIT Lincoln Laboratory (Lexington, MA)
- …has implemented vertically integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg, ... of a multi-disciplinary team responsible for the design and layout of lithographic masks for silicon-based, compound-semiconductor, and heterogeneous/hybrid… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Mask Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... and highly motivated engineers to work on the physical layout design and development of our next generation custom...members on the new process technologies to design the layout of high-speed memory macros. You will have the… more
- Capgemini (Minneapolis, MN)
- …* Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout * Utilizing advanced CAD tools and mask design knowledge to deliver correct ... **About the job you're considering** * 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent… more
- MIT Lincoln Laboratory (Lexington, MA)
- … layout changes. The engineer will collaborate with others involved in mask layout from basic layout cell creation and floor-planning to final ... has implemented vertically integrated in-house resources to facilitate design, lithographic mask layout , material growth and characterization, fabrication (eg,… more
- Texas Instruments (Dallas, TX)
- **Change the world. Love your job.** A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices ... performance targets. **Responsibilities include:** As a Resolution Enhancement Techniques (RET) Engineer , you'll architect new TI products and make our customers'… more
- Texas Instruments (Dallas, TX)
- **Change the world. Love your job.** A Process Development Engineer is responsible for the development, characterization and optimization of MEMS resonator devices ... performance targets. We are seeking a highly skilled and motivated OPC/DFM Engineer to join our RET (Resolution Enhancement Techniques) team in Advanced Technology… more
- Micron Technology, Inc. (Richardson, TX)
- …ever. We are excited to provide an outstanding opportunity for a Staff CAD Engineer to join our Engineering Automation (EA) organization at Micron. This role is ... and methodologies for next-generation memory designs. Collaborating closely with design, layout , verification, modeling, and process teams, you will be integral in… more
- Northrop Grumman (Linthicum Heights, MD)
- …your career today. Northrop Grumman Mission Systems is seeking a **Semiconductor Equipment Engineer Level 3 / 4** for our Advanced Technology Lab (ATL) - located ... ATL is responsible for all aspects of semiconductor technology including design, mask making, wafer fabrication, test, and assembly. The Semiconductor Equipment … more