- Microsoft Corporation (Austin, TX)
- …and optimize the Cloud infrastructure. We are looking for a **Principal Logic Design Engineer ** to join the team. \#SCHIE **Responsibilities** + Establish ... Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP. + Collaborate with...meets both architectural and micro-architectural intent. + Interface with physical design (PD), design for… more
- NVIDIA (Santa Clara, CA)
- … by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure a ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design ...+ Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals.… more
- Micron Technology, Inc. (Folsom, CA)
- …communicate and advance faster than ever. We are searching for a High Speed I/O Design engineer at our Micron Technology's HBM Team in Folsom, California. As a ... high speed Design engineer , you will be working for...minimize source of clock jitter. + Determine sources of timing variation + Establish timing budgets related… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...analysis on the design . + Drive the design and physical implementation of digital and/or… more
- Capgemini (Austin, TX)
- **About the job you're considering** Looking for experienced Electrical design validation engineer for validating the power and high speed interfaces in hardware ... + Knowledge on schematics and layout design tools like Orcad, Allegro, DxDesigner, Design Entry HDL, Mentor Physical viewer, Valor, GC Preview tools + Good… more
- General Atomics (Boston, MA)
- …industrial, and commercial customers worldwide. We are currently hiring a Senior Electrical Engineer (EE) who will be a key member within the GA-EMS Radar ... in support of new air and ground-based radar products. The Senior Electrical Engineer will report to the Manager of Hardware Engineering within the Radar… more
- NVIDIA (Santa Clara, CA)
- …System Verilog, logic design concepts, and typical structures. + Good understanding of design for test, timing constraints, and static timing analysis. + ... be translated into RTL and firmware designs. For backend design , you will define, build synthesis constraints and drive..., you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and… more
- Silvus Technologies (Los Angeles, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Google (Fremont, CA)
- Staff Silicon Design Engineer , Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... Verilog or SystemVerilog. + Experience of synthesis and static timing analysis. + Experience in silicon validation of ASICs,...Raxium is seeking a highly motivated and skilled Digital Design Engineer with expertise in SystemVerilog to… more
- The Boeing Company (Mountain View, CA)
- … practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us as part… more