- BAE Systems (Manchester, NH)
- …all stages of FPGA and/or ASIC development including requirements management, RTL design, verification, synthesis, timing analysis, lab bring up/validation + ... Experience working within a team of FPGA Design and Design Verification engineers + Proficient in VHDL (preferred) or Verilog HDL coding + Familiarity with AMD Vivado/Vitis or Altera Quartus + Proficient in MS-Project, MS-Word, MS-Excel **Preferred Education,… more
- Micron Technology, Inc. (Richardson, TX)
- …design and device physics + Experience reading schematics, timing diagrams, and RTL + Familiarity with FineSim and/or HSPICE, SystemVerilog, and scripting languages ... (Python/Tcl/Perl) + Strong analytical problem-solving skills and ability to work in cross-disciplinary teams **Preferred Qualifications** + Familiarity with memory design (DRAM/HBM/SRAM) and SoC/IO interfaces + Experience with data analysis or scripting to… more
- Amazon (Sunnyvale, CA)
- …through the various design phases of Silicon development from architecture definition, RTL design, Verification, IP design, Physical design, silicon bring up, test, ... characterization, quality, reliability and post silicon management. About the team Basic Qualifications - 5+ years of technical product or program management experience - 7+ years of working directly with engineering teams experience - 3+ years of software… more
- Google (Poughkeepsie, NY)
- …Provide CPU front-end designs, emphasizing on microarchitecture and Register-Transfer Level ( RTL ) design for the next generation CPU. + Propose performance enhancing ... microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements and facilitate final decision making. + Deliver designs that meet Power,… more
- Applied Materials (Santa Clara, CA)
- …* Design and implement FPGA logic using Vivado, IP Integrator, and Vitis. * Develop RTL modules in VHDL/Verilog for Zynq PL or Xilinx FPGA. * Build and integrate ... custom IP cores and AXI interfaces. * Implement HW-SW co-design using ARM processors on Zynq SoCs. * Implement xDMA, memory IP to realize data transfer between PS and PL. * Implement high-speed IO to realize data transfer between different FPGAs. **CMOS Sensor… more
- Amazon (Austin, TX)
- …improved upon, documented, tested, and reused - Close collaboration with RTL designers, design verification engineers, other software teams and customers Basic ... Qualifications - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at… more
- SpaceX (Redmond, WA)
- …Engineering, Computer Engineering or Computer Science + 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: + ... ASIC/FPGA system integration experience + Proficiency in Python, C/C++, and Bash + Experience in designing DSP, digital communication system datapath blocks, and/or modem design + Experience with EDA tools such as HDL simulators (eg VCS, Questa, IES), HDL Lint… more
- Oracle (Santa Clara, CA)
- …+ _Experience with Simulation/Verification tools such as Synopsys VCS._ + _Experience with RTL linter tools such as Real Intent's Ascent Lint._ + _Experience with ... I2C/SPI/eSPI/PMBUS/SVID/SGPIO/etc communication bus is preferred._ + _Strong knowledge and application of high-speed design methodologies for FPGA logic._ + _Solid understanding of digital design principles and synchronous design techniques._ + _Experience… more
- Oracle (Santa Clara, CA)
- …experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. \#LI-SM18 Disclaimer: **Certain US customer or client-facing roles may ... be required to comply with applicable requirements, such as immunization and occupational health mandates.** **Range and benefit information provided in this posting are specific to the stated locations only** US: Hiring Range in USD from: $120,100 to $251,600… more
- Broadcom (San Jose, CA)
- …as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. **Key Responsibilities** + Bandwidth & ... Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). +… more
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