• Sr. ASIC Design Engineer, Cloud-Scale Machine…

    Amazon (Austin, TX)
    …you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications. - Analyze design, microarchitecture or ... performance or area requirements. - Develop micro-architecture, implement SystemVerilog RTL , and deliver synthesis/timing clean design with constraints. - Perform… more
    Amazon (12/30/25)
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  • ASIC Hardware Design Engineer - New College Grad

    NVIDIA (Austin, TX)
    …integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs. + ... the guidance of senior engineers. + Learn and run RTL checks to ensure design quality (eg, cross clock...clocks, reset, latency, and more). + Design and implement RTL features (microarchitecture and RTL ) with mentorship… more
    NVIDIA (12/10/25)
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  • Senior Engineer, Front End Computer Aided Design

    Microsoft Corporation (Mountain View, CA)
    …solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design, Design Verification, Validation, DFT, Emulation, Design Synthesis, ... RTL Power Anaysis, PD Handoff and SoC integration. This...Timevision, Fishtail, Formality/LEC, Genus, Fusion Compile. - Expertise in RTL power/UPF linting flows like Power Artist/Jules, VCLP. -… more
    Microsoft Corporation (12/03/25)
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  • Senior ASIC Design Engineer - Hardware

    NVIDIA (Austin, TX)
    …integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs + ... applying the performance monitoring system + Run and debug RTL checks to ensure design quality (eg, cross clock...clocks, reset, latency, and more) + Design and implement RTL features (microarchitecture and RTL ) + Work… more
    NVIDIA (11/21/25)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant ... in-system test, debug and diagnostics needs of the design. + Lead the RTL implementation from the architecture specifications and required RTL quality checks… more
    Cisco (11/12/25)
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  • HBM SOC Design Engineer

    Micron Technology, Inc. (Richardson, TX)
    …successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, high-performance computing ... to help create high-quality specifications. + Writing specifications, developing RTL , integrating IP, testing code, debugging failures, running static checks… more
    Micron Technology, Inc. (10/15/25)
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  • Senior Software Engineer, Hardware Tools…

    NVIDIA (Santa Clara, CA)
    …a dedicated and motivated Software developer with particular interest in algorithms and RTL Design. Understanding both Software and Hardware principles will be a key ... doing: + Architect, design, develop and support tools for RTL generation across all NVIDIA products + Architect automated...automated connectivity, auto logic insertion and post processing Verilog RTL + Improve quality of existing tools and flows… more
    NVIDIA (10/11/25)
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  • Physical IC Design Engineer

    Broadcom (San Jose, CA)
    …require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out. **Responsibilities include, but are not limited to the ... Physical Verification, and Timing Closure + Setup and Synthesizing RTL + Timing closure through various methods and strategies...Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in person at our… more
    Broadcom (12/18/25)
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  • Senior ASIC Physical Design Engineer

    Google (Sunnyvale, CA)
    …practical experience. + 7 years of experience with physical design (eg from RTL to GDSII, including key stages like floorplanning, place and route, and timing ... an ASIC Physical Design Engineer, you will collaborate with RTL , Design for Testing (DFT), Floorplan, and full-chip Signoff...closure of the full chip and individual blocks from RTL -to-GDS. + Collaborate with internal logic and internal and… more
    Google (12/18/25)
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  • Sr. SoC Power Engineer, Annapurna Labs - Cloud…

    Amazon (Austin, TX)
    …level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine ... power analysis & modelling at various stages of design ( RTL to gate level netlist) - Develop and maintain...PowerArtist or similar - Ability to give feedback to RTL designers and Physical Designers on how to reduce… more
    Amazon (12/17/25)
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