• Principal Digital Design Engineer

    Renesas (Duluth, GA)
    Principal Digital Design Engineer Job Description + Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit + Contribute as part ... designs and writing device-level or sub-system specifications. + **Fluent in Verilog RTL coding and ASIC design methodology** + Expertise in digital design… more
    Renesas (12/12/25)
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  • Sr. Design Engineering Architect - Front End

    Cadence Design Systems, Inc. (Austin, TX)
    …be responsible for: Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & ... for IPs and subsystems, ensuring they meet PPA goals. RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex… more
    Cadence Design Systems, Inc. (12/10/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
    NVIDIA (12/09/25)
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  • Staff Lead Design Verification Engineer

    Northrop Grumman (Jessup, MD)
    …(High Speed Serial). Other responsibilities will include: **Design Entry & RTL Development:** + Create comprehensive test-benches for behavioral simulation + Design ... implement verification strategies for complex digital systems + Ensure RTL implementation meets precise design specification requirements **Functional Verification:**… more
    Northrop Grumman (12/05/25)
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  • FPGA Development Engineer, Bespoke Solutions

    Amazon (Arlington, VA)
    …for which they perform AWS work. 10012 Key job responsibilities - Develop custom RTL and integrate with third party libraries to build end to end 100G+ solutions. ... software to interact with custom hardware. You will debug RTL in simulation, synthesize and implement ensuring it meets...it meets timing and performance requirements. You help deploy RTL onto hardware targets and help debug issues that… more
    Amazon (12/03/25)
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  • Principal/Sr. Principal Digital Engineer (FPGA)

    Northrop Grumman (Cincinnati, OH)
    …life cycle process. In this capacity, you will utilize your working knowledge of RTL and digital interfaces. The ideal candidate will have experience with: + RTL ... 0 years with a PhD + Demonstrated proficiency in RTL modeling and simulation (experience within past 3 years)...4 years with a PhD + Demonstrated proficiency in RTL modeling and simulation (experience within past 3 years)… more
    Northrop Grumman (11/29/25)
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  • ASIC Design Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …vital part of the GPU Design team, detailing, implementing, and delivering verified RTL to meet design targets. + Analyze architectural trade-offs based on features, ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. + Support… more
    NVIDIA (11/25/25)
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  • ASIC Digital Design Engineer

    Teledyne (Goleta, CA)
    …and block diagrams. + Creating risk assessments and traceability matrices. + RTL Front-End Design + Behavioral modeling of digital controllers (eg, pixel readout ... for ASIC modes. + Clock domain crossing and power-aware RTL coding (asynchronous resets, and multi-clock domains). + Modular...corners. + DRC, LVS, extraction and signoff. + Perform RTL Verification & Simulation as needed + Functional verification… more
    Teledyne (11/21/25)
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  • Senior CPU Power Architect

    NVIDIA (Santa Clara, CA)
    …- from early modeling to silicon validation. You will collaborate with architecture, RTL , physical design, and validation teams to ensure our CPUs meet aggressive ... + Pre-silicon Power Estimation: Model and estimate CPU power at C-model, RTL , and netlist stages using industry-standard tools. + Power Optimization: Identify… more
    NVIDIA (11/20/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
    NVIDIA (11/20/25)
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