- NVIDIA (Santa Clara, CA)
- …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
- NVIDIA (Santa Clara, CA)
- …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
- Northrop Grumman (Linthicum Heights, MD)
- …methods, tools and techniques. + Perform functional verification of register transfer level ( RTL ) code of a complex ASIC at block level and SOC level using ... + Experience developing testplans, participating in reviews, test development and RTL debug **Basic Qualifications for a** **Senior Principal Engineer:** +… more
- RTX Corporation (Cedar Rapids, IA)
- …Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend new tools and ... of a degree, 9 years of relevant experience + RTL coding and simulation in VHDL or Verilog +...timing closure + Testbench development for the verification of RTL blocks using VHDL or System Verilog. + Experience… more
- Broadcom (Irvine, CA)
- …and/or system requirements prepare detailed design document, timing constraint file RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL ... solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis. In-depth knowledge for design for low power and design… more
- NVIDIA (Westford, MA)
- …a significant impact! What you'll be doing: + Run integration flows to build RTL , run connectivity checks, and assemble logical units. + Perform linting checks and ... debug RTL and netlist-level issues. + Collaborate with front-end teams...connectivity issues and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows.… more
- Broadcom (Colorado Springs, CO)
- …knowledge and expertise towards DFT related aspects of IC Design through RTL and netlists. **Responsibilities include, but are not limited to the following:** ... ATPG + Hierarchical DFT Flow and Methodology Development + Collaborating with IC Design RTL Engineers and Physical Design Engineers + Must work in person at our… more
- Google (Sunnyvale, CA)
- …AI/ML-driven systems. As a Physical Design Engineer, you will collaborate with RTL , design for testing (DFT), floorplan, and full-chip Signoff teams. Additionally, ... design and closure of the subchip and individual blocks from RTL -to-GDS. + Collaborate with RTL /Design and physical design (PD) teams to achieve the best… more
- NVIDIA (Santa Clara, CA)
- …+ You are expected to come up with micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. + Support post-silicon ... working on ASIC design and development. + Experience in micro-architecture and RTL development of complex designs in Verilog. + Exposure to Digital systems… more
- Cisco (Maynard, MA)
- …Physical Design Engineer, you will play a key role in the full RTL -to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning ... high-performance networking chips. You will: * Own and drive RTL -to-GDSII implementation for advanced nodes (sub-7nm to 2nm) *...and manage timing ECO strategies * Collaborate closely with RTL and DFT designers to debug and root-cause physical… more