• FPGA Engineer - Design

    Insight Global (Saratoga, CA)
    …providing strategic direction and implementation in the following areas: * Own FPGA RTL development from blank sheet to flight. * Develop FPGA logical architecture ... HW/SW interfaces between fabric logic and processing subsystems. * Develop FPGA RTL code for Microsemi FPGAs and other manufacturer SoCs in either SystemVerilog… more
    Insight Global (12/07/25)
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  • Senior ASIC Engineer - SDC

    Cisco (San Jose, CA)
    …fullchip timing in multiple timing modes. + Option to also do block level RTL design or block or top-level IP integration. + Helping develop efficient methodology to ... cycle. + Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. + Creating fullchip clocking diagrams and related… more
    Cisco (12/03/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …the right trade-offs. Key job responsibilities - Work with RTL /logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs ... other physical design engineers as well as with the RTL /Arch. teams About the team Inclusive Team Culture Here...- 6+ years in ASIC Physical Design from - RTL -to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm -… more
    Amazon (12/02/25)
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  • Senior ASIC Design Engineer - Circuits

    NVIDIA (Santa Clara, CA)
    …the power and performance of NVIDIA's next generation GPUs + Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality ... digital IPs. + Craft and develop behavioral models in RTL for mixed-signal blocks. What we need to see:...understanding of physical design and VLSI + Experience with RTL development, Custom Digital Design, and Behavioral Circuit Modeling… more
    NVIDIA (11/26/25)
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  • Staff Logic Circuit Design Engineer

    Micron Technology, Inc. (Folsom, CA)
    …inspiring the world to learn, communicate and advance faster than ever. A HBM RTL designer will need to have significant experience front end digital design! The ... validation. **Responsibilities** + Define requirements, develop specifications, and architect RTL blocks for HBM products. + Own circuit development, simulations,… more
    Micron Technology, Inc. (11/20/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    …looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing ... design quality checks and reviews to present the physical design team with high-quality RTL What we need to see: + A Masters in Computer or Electrical Engineering… more
    NVIDIA (11/20/25)
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  • Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …with cross-functional teams to deliver industry-leading solutions. **Key Responsibilities** + ** RTL Design & Microarchitecture** + Develop synthesizable RTL ... in digital logic design for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design** . + Experience with one or more of the following protocols:… more
    Teledyne (11/18/25)
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  • Senior Datacenter Resiliency Architect

    NVIDIA (Santa Clara, CA)
    …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
    NVIDIA (11/15/25)
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  • Digital Design: SerDes Digital IP Design Engineer

    Broadcom (Fort Collins, CO)
    …and documentation for SerDes development. Performs architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and ... Knowledge of all aspects of the process flow from high-level RTL design to synthesis, RTL / netlist audits (using tools such as Spyglass), Formal verification,… more
    Broadcom (11/12/25)
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  • Senior ASIC Design Engineer - Clocks IP

    NVIDIA (Santa Clara, CA)
    …and Ease of timing closure to innovate and implement new Clocking topologies in RTL . + Collaborate with Physical design and timing team to evaluate Clocking concerns ... + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team,...ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis. + Strong… more
    NVIDIA (10/28/25)
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