• Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …with cross-functional teams to deliver industry-leading solutions. **Key Responsibilities** + ** RTL Design & Microarchitecture** + Develop synthesizable RTL ... in digital logic design for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design** . + Experience with one or more of the following protocols:… more
    Teledyne (11/18/25)
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  • Senior Datacenter Resiliency Architect

    NVIDIA (Santa Clara, CA)
    …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
    NVIDIA (11/15/25)
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  • Digital Design: SerDes Digital IP Design Engineer

    Broadcom (Fort Collins, CO)
    …and documentation for SerDes development. Performs architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and ... Knowledge of all aspects of the process flow from high-level RTL design to synthesis, RTL / netlist audits (using tools such as Spyglass), Formal verification,… more
    Broadcom (11/12/25)
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  • Senior ASIC Design Engineer - Clocks IP

    NVIDIA (Santa Clara, CA)
    …and Ease of timing closure to innovate and implement new Clocking topologies in RTL . + Collaborate with Physical design and timing team to evaluate Clocking concerns ... + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team,...ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis. + Strong… more
    NVIDIA (10/28/25)
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  • Senior FPGA Design Engineer (Hybrid-Puerto Rico)

    RTX Corporation (Aguadilla, PR)
    …+ Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend new tools and ... to access information under this program/contract. **Qualifications We Prefer:** + RTL coding and simulation in VHDL, Verilog, or SystemVerilog experience +… more
    RTX Corporation (10/18/25)
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  • Principal Electrical Engineer - ASIC/FPGA (Onsite)

    RTX Corporation (Salt Lake City, UT)
    …Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend new tools and ... to a government security investigation/reinstatement and must meet eligibility requirements + RTL coding and simulation in Verilog or VHDL + Digital circuit… more
    RTX Corporation (10/16/25)
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  • Senior Applications Engineer - DDR Design IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …teams to win opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP demos to customers* Travel ... on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design* Knowledge of AXI,… more
    Cadence Design Systems, Inc. (01/10/26)
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  • Senior Firmware Verification Engineer

    Renesas (Austin, TX)
    …+ Run simulations and debug issues in pre-silicon environments, including RTL simulations and emulation platforms. + Support post-silicon bring-up, validation, and ... experience developing or using SystemVerilog testbenches. + Working familiarity with hardware RTL or digital subsystem design. + Strong programming skills in C for… more
    Renesas (01/09/26)
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  • Senior Physical Design Engineer

    Microsoft Corporation (Hillsboro, OR)
    …checks across block, subsystem, and top level. + Coordinate with CAD, RTL /Design teams/DFT, Architecture team, Foundry interface team, Technology team & other ... PERC and ESD analysis, RDL implementation and bump planning. + Knowledge of RTL to GDS implementation in Physical Design domain. + Hands-on experience with… more
    Microsoft Corporation (01/09/26)
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  • Principal Physical Design Engineer

    Microsoft Corporation (Hillsboro, OR)
    …for SOC Top Level Design Planning and partitioning strategies. + Responsible for RTL to GDS implementation in Physical Design domain. + Coordinate with CAD, ... RTL /Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential. + Lead & influence design tools,… more
    Microsoft Corporation (01/09/26)
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