• ASIC Design Engineer - New College…

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Engineer ! NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's ... impact on the world. Join NVIDIA as an ASIC Design Engineer , influencing product lines spanning consumer...interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design ,… more
    NVIDIA (11/25/25)
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  • Principal Digital Design Engineer

    Renesas (Duluth, GA)
    Principal Digital Design Engineer Job Description + Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit + ... writing device-level or sub-system specifications. + **Fluent in Verilog RTL coding and ASIC design methodology** +...**Fluent in Verilog RTL coding and ASIC design methodology** + Expertise in digital design more
    Renesas (12/12/25)
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  • ASIC Digital Design Engineer

    Teledyne (Goleta, CA)
    …being on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer : Oversees definition, design , verification, and documentation ... block diagrams. + Creating risk assessments and traceability matrices. + RTL Front-End Design + Behavioral modeling of digital controllers (eg, pixel readout… more
    Teledyne (11/21/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position ... interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis.… more
    NVIDIA (12/09/25)
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  • Physical IC Design Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position ... + Floor-planning and Layout + Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in person at our San Jose site: no remote… more
    Broadcom (12/10/25)
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  • Senior ASIC Engineer , IP Design

    Google (San Diego, CA)
    …related field, or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with ... Senior ASIC Engineer , IP Design , Silicon _corporate_fare_ Google...estimation, timing closure, synthesis. + Experience with methodologies for RTL quality checks (eg, Lint, CDC, RDC). **About the… more
    Google (12/06/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …must be completed prior to joining Meta 8. 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration ... **Summary:** As a Digital Design Engineer at Meta Reality Labs,...Responsible for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan… more
    Meta (10/18/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    …team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate ... We are now looking for a CPU Design Methodology Engineer ! The complexity of...+ Excellent analytical and problem-solving skills + Experience in RTL design (Verilog), verification (UVM, System Verilog),… more
    NVIDIA (11/20/25)
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  • Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …and networking. **Role Overview** We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team ... measurement products. Join our high-speed Protocol Team as a **Staff** **Logic Design Engineer ** , where you'll architect and implement high-performance digital… more
    Teledyne (11/18/25)
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  • ASIC Design Engineer - New College…

    NVIDIA (Santa Clara, CA)
    …in micro-architecture and RTL development (Verilog). + Good understanding of ASIC design flow including RTL design , verification, logic synthesis and ... document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs based on… more
    NVIDIA (11/18/25)
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