• Electrical Engineer II - ASIC/ FPGA

    RTX Corporation (El Segundo, CA)
    …requirements capture and ASIC / FPGA digital architecture + Implement ASIC / FPGA digital design using RTL + Support verification and system integration ... security clearance is required prior to start date + RTL coding and simulation in VHDL, Verilog, or SystemVerilog...equipment **Qualifications We Prefer:** + Experience using ASIC and/or FPGA design tools (eg Modelsim, Quartus, Vivado… more
    RTX Corporation (10/28/25)
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  • FPGA Design Engineer

    University of Rochester (Rochester, NY)
    …consumer off the shelf (COTS) products deployed across the lab. We are seeking an experienced FPGA design engineer to aid in the development of new solutions ... Strong working knowledge of VHDL coding - Experience with RTL simulation - Familiarity with circuit design ,...with RTL simulation - Familiarity with circuit design , development, and troubleshooting Desired skills or experience includes:… more
    University of Rochester (11/06/25)
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  • Senior FPGA Engineer

    RTX Corporation (Cambridge, MA)
    …absence of a degree, 9 years of relevant experience + Professional experience in FPGA development processes: RTL design , verification, timing analysis, board ... citizens are eligible for a security clearance **Security Clearance:** DoD Clearance: Secret ** FPGA Engineer , P3** **Who We Are** RTX Corporation is an Aerospace… more
    RTX Corporation (11/19/25)
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  • Cpld/ FPGA Firmware Engineer

    Amazon (Austin, TX)
    …delighted customers, Annapurna is a fantastic choice. We are seeking an experienced CPLD/ FPGA Firmware Engineer to join our ML Acceleration Server Firmware team, ... Description Annapurna Labs is at the forefront of hardware/software co- design , not just in Amazon Web Services (AWS) but...at scale. Key job responsibilities - Develop CPLD and FPGA programs that implement power sequencing and manage various… more
    Amazon (12/09/25)
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  • Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …logic design for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design ** . + Experience with one or more of the following protocols: ... and networking. **Role Overview** We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team… more
    Teledyne (11/18/25)
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  • Staff Lead Design Verification…

    Northrop Grumman (Jessup, MD)
    …Languages: (Verilog, VHDL, SystemVerilog) + Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage ... & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team.... We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies.… more
    Northrop Grumman (12/05/25)
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  • Engineer IV

    General Atomics (Englewood, CO)
    …and academic mission requirements. General Atomics is seeking a highly experienced and motivated FPGA Design Engineer to join our team. The successful ... Required?:** Yes **Pay Range High:** 171,398 **Recruitment Posting Title:** FPGA Design Engineer **Job Qualifications:**...in lieu of education. **Required Experience:** + Expertise in FPGA design , including RTL coding… more
    General Atomics (12/11/25)
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  • Senior Digital Design Engineer

    BrainChip, Inc. (Laguna Hills, CA)
    BrainChip is seeking a Senior Digital Design Engineer to join a team working on cutting-edge and novel AI hardware. The primary job function is to work with team ... part of our Hardware Development group. The Sr. Digital Design Engineer needs to be able to...tools to check the functionalities of the designs in RTL and gate level. Collaborate with other… more
    BrainChip, Inc. (12/11/25)
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  • Senior ASIC Engineer , IP Design

    Google (San Diego, CA)
    …related field, or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with ... Senior ASIC Engineer , IP Design , Silicon _corporate_fare_ Google...estimation, timing closure, synthesis. + Experience with methodologies for RTL quality checks (eg, Lint, CDC, RDC). **About the… more
    Google (12/06/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …must be completed prior to joining Meta 8. 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration ... **Summary:** As a Digital Design Engineer at Meta Reality Labs,...Responsible for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan… more
    Meta (10/18/25)
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