- Lockheed Martin (Chelmsford, MA)
- **Description:** You will be the Electrical Design Engineer for Lockheed Martin's Chelmsford, MA campus\. Our team drives cutting edge digital and FPGA ... systems\. **What You Will Be Doing** As the Electrical Design Engineer you will create and verify...with development boards from AMD/Xilinx, Microsemi or Intel\. \-Some FPGA design skills using software tools such… more
- Broadcom (Irvine, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... including micro-architecture definition + Perform RTL design using Verilog HDL, with an...ECO implementation. + Support system level validation efforts on FPGA /emulation + Support silicon bring-up and debug efforts **Job… more
- Amazon (Sunnyvale, CA)
- …TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and architecture team ... with team members across multiple disciplines * Develop detailed design specifications and documentation * Perform RTL ...defining clock domains and power domains - Knowledge of FPGA and emulation platforms - Knowledge of SoC architecture… more
- NVIDIA (Austin, TX)
- …approaches to deliver bug-free board and system designs. + Board and system level RTL design . + Simulation and emulation of model development for board level ... role, you will bring to bear your knowledge of RTL verification and system design to develop...layout and timing checks. + Collaborate with architecture, ASIC, FPGA , mixed signal, software and system design … more
- Northrop Grumman (Linthicum Heights, MD)
- …in Mission Systems that encompasses Digital Verification Engineering to support ASIC and FPGA product development. + Work closely with design and verification ... development and RTL debug **Basic Qualifications for a** **Senior Principal Engineer :** + Bachelor's degree with 8 years of experience, a Master's degree with… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...requirements and system limitations + Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level… more
- ManpowerGroup (Redmond, WA)
- …C/C++, Python, Perl, and/or PowerShell for scripting and automation. + Experience with RTL design and verification, including CDC, lint, and synthesis. + ... leader in the semiconductor industry, is seeking a Hardware Design & Validation Engineer - AI Semiconductor...Contract **Pay Range:** Not disclosed **What's the Job?** + Design , implement, and verify RTL blocks for… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * Knowledge of ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP… more
- SpaceX (Hawthorne, CA)
- …using the Xilinx toolchain + Experience with verification between simulation and RTL FPGA implementation + Experience modeling RF and channel impairments ... and sensing systems + Work across disciplines with RF/antenna, FPGA , and software engineers to design and...validate overall system performance, including modem performance + Support FPGA designers with bit-accurate and cycle-accurate RTL … more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more