- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT,… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... **Sr. ASIC Engineer** The application window is expected to...refining design and timing constraints for seamless physical design closure. As part of this… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Reset and Boot ASIC Engineer...doing: + Be an integral part of the System ASIC Design team to help with the ... functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design...CHI + Familiar with OCP secure boot specification and physical security handling process + Possess design … more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... . + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers to...high bandwidth data paths. + A deep understanding of ASIC design flows including RTL design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... , Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with...+ Strong familiarity and experience with all stages of ASIC design flow including front end … more
- NVIDIA (Santa Clara, CA)
- …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more
- Palo Alto Networks (Santa Clara, CA)
- …CE, or CS (MSEE or equivalent military experience preferred). + 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production. + Solid ... from specification through silicon bring-up, working with world-class verification and physical - design engineers to hit aggressive performance, power, and… more
- SanDisk (Milpitas, CA)
- …+ Coordinate effectively with SoC Design , SoC Design Verification, ASIC Validation, DFT, Physical Design , Hardware, Mixed Signal IPs, Foundry, ... + Maintain and enforce the highest industry standards and best practices in ASIC design development. Provide mentorship and guidance to team members, fostering… more
- SpaceX (Redmond, WA)
- …to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer/ Senior : $200,000.00 - $270,000.00/per year Your actual ... Principal ASIC Design Engineer (Silicon Engineering) Redmond,...Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check) +… more
- NVIDIA (Austin, TX)
- Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering ... by others + Hands- on silicon debug is a plus. + Exposure to physical design With competitive salaries and a generous benefits package, we are widely considered… more