• Senior System SW Engineer, System…

    Palo Alto Networks (Santa Clara, CA)
    …innovation and collaboration, to execution. From showing up for each other with integrity to creating an environment where we all feel included. As a member ... few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is...Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC more
    Palo Alto Networks (09/19/25)
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  • Senior Package Layout Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    NVIDIA's GPUs and SOCs are the world leaders in power , performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to ... To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making...Layout team, you will collaborate to implement high speed/density ASIC packages. + Perform substrate breakout patterns for … more
    NVIDIA (10/08/25)
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  • Senior Hardware SoC Architect

    NVIDIA (Santa Clara, CA)
    …Detailed knowledge at least one of: 1) PLLs, DLLs, etc, 2) clock-related signal integrity effects, or 3) platform power and reset sequencing + Automotive ... We are now looking for a Senior Hardware SoC Architect! Do you want to...chip. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design, VLSI and platform teams.… more
    NVIDIA (08/22/25)
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  • Senior Hardware Systems Design…

    NVIDIA (Austin, TX)
    …+ Background of system validation & model to hardware correlation + Background of signal/ power integrity + Knowledge of AI/ML to help with workflows Your base ... connectivity, design rule, layout and timing checks. + Collaborate with architecture, ASIC , FPGA, mixed signal, software and system design teams to develop end… more
    NVIDIA (09/25/25)
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  • Senior Analog/mixed-signal IC Design…

    Cisco (San Jose, CA)
    …You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met. + You will develop high speed AMS ... Senior Analog/mixed-signal IC Design Engineer - Acacia Apply...products. We optimize design that will integrate into the ASIC . Our team interacts with other Acacia groups including… more
    Cisco (10/11/25)
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  • Senior Mechanical Engineer

    Cisco (San Jose, CA)
    Senior Mechanical Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1446721) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... series. The Cisco 8000 series utilizes Cisco's revolutionary Silicon One ASIC that delivers unmatched performance and density with feature-rich functionality. We… more
    Cisco (09/22/25)
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  • Senior Product Manager (Post-Quantum VPN…

    Palo Alto Networks (Santa Clara, CA)
    …innovation and collaboration, to execution. From showing up for each other with integrity to creating an environment where we all feel included. As a member ... few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is...**Your Career** Palo Alto Networks is seeking a visionary Senior Product Manager to drive the evolution of our… more
    Palo Alto Networks (09/20/25)
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  • Senior Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …engineers to help achieve that mission. We are looking for a ** Senior ** **Design Engineer** to work in the dynamic Microsoft Artificial Intelligence System ... Each day we build on our values of respect, integrity , and accountability to create a culture of inclusion...experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/SOC designs. + 4+ years of experience in Synthesis,… more
    Microsoft Corporation (10/11/25)
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  • Sr. SerDes Characterization and Validation…

    SpaceX (Irvine, CA)
    …test coverage + Work closely with electrical design team to review signal integrity , power integrity and radiated/conducted emissions concerns as well ... extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: ASIC Validation Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level… more
    SpaceX (10/06/25)
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  • Analog Mixed-Signal Design Engineer

    Broadcom (San Jose, CA)
    …EDA integration, foundry PDK and associated collaterals. + Good understanding of signal integrity and power integrity . + Good understanding of design ... you apply.** **Job Description:** Broadcom is looking for a senior level analog mixed-signal designer. In this highly visible...a PhD + Experience in designing low jitter, low power PLL, VCO and clocking circuitry. Experience with analog… more
    Broadcom (10/10/25)
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