• Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Strong familiarity and experience with all stages of ASIC design flow including front end design and verification,...flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding interpersonal… more
    NVIDIA (11/26/25)
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  • Principal ASIC Design Engineer

    SpaceX (Redmond, WA)
    …to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer / Senior : $200,000.00 - $270,000.00/per year Your actual ... Principal ASIC Design Engineer (Silicon Engineering) Redmond,...that in top level and deliver the fully verified, synthesis/ timing clean design + Work closely with verification team… more
    SpaceX (01/01/26)
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  • Senior ASIC Design Engineer

    Palo Alto Networks (Santa Clara, CA)
    …and the kind of precision that drives great outcomes. **Your Career** Join our ASIC team and help deliver the digital logic that powers our next-generation firewall ... and add design-for-debug features. + **Partner** with physical-design teams: review synthesis/ timing reports, rewrite RTL to close critical paths, and consult on… more
    Palo Alto Networks (12/15/25)
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  • Senior Engineer - FPGA/ ASIC

    BAE Systems (Huntsville, AL)
    …Other incentives may be available based on position level and/or job specifics. ** Senior Engineer - FPGA/ ASIC Design (Hybrid)** **117732BR** EEO Career ... systems for Department of Defense (DoD) applications. As a Senior Design Engineer , you will have the...with design standards and best practices + Perform static timing analysis, simulations, and integration testing to ensure design… more
    BAE Systems (10/24/25)
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  • Senior ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and ... in design methodologies and EDA tools - Experience working with Synthesis, timing closure, and design constraints Preferred Qualifications - Experience with ARM and… more
    Amazon (12/12/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... architects, platform, and software teams. + Partner with design, verification, synthesis, timing , and backend teams to ensure cohesive integration. + Create and… more
    NVIDIA (10/25/25)
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  • Senior ASIC Physical Design…

    NVIDIA (Santa Clara, CA)
    …on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on ... Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the unit....expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT,… more
    NVIDIA (11/20/25)
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  • Sr. ASIC Design Engineer

    Amazon (Austin, TX)
    …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
    Amazon (12/30/25)
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  • Senior DSP and ASIC Engineer

    Broadcom (Irvine, CA)
    …Account, please Sign-In before you apply.** **Job Description:** Looking for a design engineer to work on challenging high speed design of complex modules for ... + Familiarity with digital chip design concepts, such as clocking, timing , pipelines, and performance vs area/power tradeoffs. **Additional Job Description:**… more
    Broadcom (11/15/25)
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  • Senior ASIC Design Engineer

    Amazon (San Diego, CA)
    …in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing customer ... constructed using UVM, System C and DPI-C . Ensure that the block meets DFT, timing and power targets by working closely with the implementation team . Learn about… more
    Amazon (11/18/25)
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