- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit. What we need to see:...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Cisco (Milpitas, CA)
- …features. **Your Impact** We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in ... the entire FPGA tool flow, including synthesis, placement, routing, and static timing analysis. Aggressively pursue timing closure to meet strict performance… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit. What we need to see:...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Silvus Technologies (Irvine, CA)
- …coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. ... (MSEE). + Basic MATLAB skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a guarantee. It is based on… more
- Microsoft Corporation (Mountain View, CA)
- …for passionate engineers to help achieve that mission. We are looking for a ** Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence ... 5+ years of experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/SOC designs. + 4+ years of experience in Synthesis, Timing … more
- NVIDIA (Santa Clara, CA)
- …looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to ... logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing … more
- Silvus Technologies (Irvine, CA)
- …coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. ... Experience using MATLAB. + Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. +… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the ... + Own Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: +… more
- Cisco (Milpitas, CA)
- …an experienced FPGA designer able to write RTL code, run simulations, address timing and other constraints, then generate programming files. You can work with many ... relevant degree and 4+ years of related experience + FPGA or ASIC development experience from specification to production. + Experience with Verilog/System Verilog… more