- NVIDIA (Santa Clara, CA)
- …fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting + Hands-on ... debug and lab tools (oscilloscopes, multimeters, logic analyzers). + Experience with ASIC power saving features and methods + Deep understanding of firmware/driver… more
- Broadcom (Fort Collins, CO)
- …Description:** Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering ... exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.… more
- Northrop Grumman (Jessup, MD)
- …culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will ... & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies into high-performance computing… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be ... data center connectivity products. **Responsibilities** **Include:** + Develop and validate timing constraints for intricate SoC designs. + Perform static timing… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and ... addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA engineering facility… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Senior Engineering Director_ in ... coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers.… more
- Honeywell (Phoenix, AZ)
- You will report directly to the Senior Engineering Manager and you'll work at our Plymouth, MN location on a Hybrid work schedule. (Other allowed Honeywell Aerospace ... (eg, S-EDA OPC jobs, Cadence Spectre SPICE simulations, Synopsys-based static timing analyses). + Construct application slurm flows to maximize batch-job license… more