• Senior Firmware Verification

    RTX Corporation (Marlborough, MA)
    …and various international customers, keeping the world safe from foreign threats. As a ** Senior Firmware Verification Engineer ** , you will be a member ... of an Integrated Program Team (IPT)) creating complex Firmware Verification solutions for Field Programmable Gate Arrays (FPGAs), System on Chip (SOC), and… more
    RTX Corporation (08/01/25)
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  • Senior ASIC Verification

    Tarana Wireless (Milpitas, CA)
    …modules that you will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to ... generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification... FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project… more
    Tarana Wireless (06/26/25)
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  • Principal Digital Verification

    Northrop Grumman (Linthicum Heights, MD)
    …career. We are looking for you to join our team as a Principal Digital Verification Engineer / Senior Principal Digital Verification Engineer based ... This requisition may be filled as a Principal Digital Engineer or a Senior Principal Digital ...cross-discipline engineering team in Mission Systems that encompasses Digital Verification Engineering to support ASIC and FPGA more
    Northrop Grumman (08/20/25)
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  • Senior Principal Design Verification

    BAE Systems (Austin, TX)
    …available based on position level and/or job specifics. ** Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **114362BR** EEO ... your skills, and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop… more
    BAE Systems (07/11/25)
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  • Senior Principal FPGA

    BAE Systems (Westminster, CO)
    …may be available based on position level and/or job specifics. ** Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR** EEO ... UVM components, and regressions/testlists. + Be responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix. +… more
    BAE Systems (08/09/25)
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  • Principal / Senior Principal FPGA

    Northrop Grumman (Annapolis Junction, MD)
    …**a Top Secret/SCI security clearance with Polygraph** **.** **Basic Qualifications Senior Principal Digital Verification Engineer :** + Bachelor's ... Secret/SCI security clearance with Polygraph** **.** **Preferred Qualifications Principal / Senior Principal Digital Verification Engineer :** + Advanced… more
    Northrop Grumman (08/08/25)
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  • Senior Digital Verification

    Huntington Ingalls Industries (Fort Meade, MD)
    …thinkers who can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs. Candidates for this ... etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface,...Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
    Huntington Ingalls Industries (07/10/25)
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  • Senior Digital Verification

    Huntington Ingalls Industries (Roanoke, VA)
    …thinkers who can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs. Candidates for this ... etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface,...Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Active Secret… more
    Huntington Ingalls Industries (07/09/25)
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  • Staff Lead Design Verification

    Northrop Grumman (Annapolis Junction, MD)
    …design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will play ... Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and...Identify and resolve signal delay and performance issues in gate timing requirements + Develop comprehensive Universal Verification more
    Northrop Grumman (07/18/25)
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  • Senior Rtl/ FPGA Design…

    Medtronic (Lafayette, CO)
    FPGA systems and components using constrained random methodologies including UVM and Formal Verification Collect and refine FPGA and SOC verification and ... a more connected, compassionate world. **A Day in the Life** Development and verification of the programmable logic elements of medical capital equipment used in… more
    Medtronic (08/21/25)
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