• System Application Engineer - Notebook

    NVIDIA (Santa Clara, CA)
    The System Application Engineer will own end‑to‑end system collateral and PoR‑driven customer support for SoC platforms, working closely with OEM and the NVIDIA ... ( eDP, DP, HDMI,PCIe, USB-C) specification, design rules and validation plan. + Serve as the technical point of...+ Drive continuous updates to design collateral based on silicon learning, field feedback, and new feature enablement. +… more
    NVIDIA (12/12/25)
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  • Principal ASIC Design Verification Engineer

    Palo Alto Networks (Santa Clara, CA)
    …You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation . We expect office-based employees to be in the ... drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that...Networking and cyber security + Formal property verification + Silicon validation - bringup, test, debug, and… more
    Palo Alto Networks (12/10/25)
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  • Senior Software Engineer

    Microsoft Corporation (Santa Clara, CA)
    …years thereafter. **PreferredQualifications:** + 1+ years of experience withpre and post silicon validation processes - Experience with Operating System (Linux ... **Overview** Microsoft Silicon , Cloud Hardware, and Infrastructure Engineering (SCHIE) is...to CPU-based alternatives. We are seeking a Senior Software Engineer to join our DPU Build and Tools team… more
    Microsoft Corporation (12/13/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... to harden controls/algorithms for next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in planning and executing our… more
    Meta (12/08/25)
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  • Optical Packaging Engineer

    Texas Instruments (Dallas, TX)
    **Optical Packaging Engineer ** **Location: Dallas, TX or Santa Clara, CA** **Group: Kilby Labs** **We can't predict what the future holds, but we know Texas ... **Kilby Labs is seeking a highly motivated and experienced Optical Packaging Engineer to lead the development and implementation of innovative packaging solutions… more
    Texas Instruments (12/01/25)
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  • ASIC Design Verification Engineer I Intern…

    Cisco (Maynard, MA)
    …Knowledge of DSP algorithms and modulation techniques such as QAM + Lab silicon validation experience + Knowledge of Formal Verification methodologies and tools ... the Team** Acacia, now part of Cisco, provides innovative silicon -based high speed optical interconnect products to accelerate network...for all. **Your Impact** The ASIC Design Verification Intern Engineer will be a member of a team working… more
    Cisco (11/20/25)
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  • ASIC Engineer , Performance & Package…

    Meta (Sunnyvale, CA)
    …Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. ... Design, Emulation and Post- Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Performance & Package… more
    Meta (11/19/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    …Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. ... Emulation and Post- Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:… more
    Meta (10/30/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    …Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. ... Emulation and Post- Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:… more
    Meta (10/30/25)
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  • SystemVerilog/UVM Design Verification…

    US Tech Solutions (Goleta, CA)
    **Job Description:** + The Verification Engineer will contribute to the pre- silicon functional verification of high-performance SoCs and related subsystems. + ... ownership of verification deliverables within a UVM/SystemVerilog environment. + The engineer will collaborate with design, architecture, and validation teams… more
    US Tech Solutions (10/14/25)
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