• Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... of several modules. + Integrate modules into the overall SOC design and work closely with other...functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design more
    NVIDIA (09/30/25)
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  • Technical Lead Manager, ASIC Design

    Google (Sunnyvale, CA)
    Technical Lead Manager, ASIC Design , Machine Learning _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision ... through tapeout. + Knowledge of high performance and low-power design techniques. + Knowledge of ASIC Verification,...For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design . **About the job** In this… more
    Google (09/29/25)
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  • Senior Video ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …for developing SoC 's. What you will be doing: + Develop ASIC designs for Video IP, including micro-architecture, design coding, performance optimization, ... We are now looking for a Senior Video ASIC Design Engineer! NVIDIA has been...timing, and area optimization, static checks, and support of physical design engineers through place and route.… more
    NVIDIA (10/15/25)
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  • Sr. ASIC Manager, Annapurna Labs

    Amazon (Cupertino, CA)
    …Basic Qualifications - Deep SOC architectural, micro architectural, chip design , verification and physical design understanding. - Experience ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...and deep knowledge in all stages of SOC design from definition to post silicon… more
    Amazon (09/30/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design more
    NVIDIA (07/31/25)
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  • ASIC Engineer, EDA Infrastructure

    Meta (Sunnyvale, CA)
    …Responsibilities: 1. Front End implementation flow development and support 2. Physical Design implementation flow development and support 3. RTL2GDS ... ASIC infrastructure to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:**...tools development and automation to help improve productivity across ASIC design cycles including but not limited… more
    Meta (09/13/25)
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  • Senior ASIC Design Engineer - Clocks…

    NVIDIA (Santa Clara, CA)
    …closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and develop ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,… more
    NVIDIA (07/29/25)
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  • ASIC Design Verification Engineer,…

    Amazon (Austin, TX)
    …Develop and execute design automation mechanisms and flows. * Work with physical design teams to achieve performance and area requirements. Mentorship & ... requirements including software applications, use models, system architecture and SoC architecture/micro-architecture solutions. * Participate in logic design more
    Amazon (09/16/25)
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  • ASIC Engineer, Implementation

    Meta (Sunnyvale, CA)
    …for Power, Performance, and Area 17. 2. Floor Planning and Placement 18. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 ... to Job" online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/ physical ...domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and… more
    Meta (09/20/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence...with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out… more
    NVIDIA (09/23/25)
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