• ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and… more
    Meta (10/30/25)
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  • Senior ASIC Design Engineer - Clocks…

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams....DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes,… more
    NVIDIA (10/28/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Austin, TX)
    Join the NVIDIA System-On-Chip ( SOC ) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering ... we need to see: + BS or equivalent experience in Electrical Engineering, Computer Engineer , or related degree required, advanced degrees (MS, PhD) a plus + 3+ years… more
    NVIDIA (11/21/25)
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  • Senior ASIC Power Engineer , ML…

    Google (Sunnyvale, CA)
    Senior ASIC Power Engineer , ML Accelerators _corporate_fare_...+ 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with ... behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on… more
    Google (12/04/25)
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  • ASIC Design Engineer - New College…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This position offers the opportunity to have real impact in a ... micro-architecture and RTL development (Verilog). + Good understanding of ASIC design flow including RTL design, verification ,...of ASIC design flow including RTL design, verification , logic synthesis and timing analysis. + Exposure to… more
    NVIDIA (11/18/25)
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  • Low Power ASIC Engineer - New…

    NVIDIA (Santa Clara, CA)
    …can make a lasting impact on the world! We are now looking for an Low Power Design/ Verification ASIC Engineer - New College Grad 2026. We continue to rapidly ... grow the research and development of energy-efficient GPU and SOC architectures. We are continually innovating in creative and...+ A strong background in Low Power architectures or verification is a plus. + Scripting abilities in Python… more
    NVIDIA (11/18/25)
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  • ASIC Design Engineer

    Meta (Sunnyvale, CA)
    …click "Apply to Job" online on this web page. **Required Skills:** ASIC Design Engineer Responsibilities: 1. Responsible for micro-architecture development. 2. ... Responsible for Lint, CDC, Synthesis, & Power Optimization. 4. Collaborate with verification and emulation teams in test planning, development, and debugging. 5.… more
    Meta (11/14/25)
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  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... at RTL & gate level and identify power reduction opportunities. 4. Run formal verification checks between RTL & gate level netlist and debug aborts, inconclusive and… more
    Meta (09/20/25)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    SoC Physical Design Engineer _corporate_fare_ Google...complex SoC . + Experience with multiple-cycles of SoC in ASIC design. + Experience with ... and its integration within AI/ML-driven systems. As a System on a Chip ( SoC ) Physical Design Engineer , you will collaborate with Register-Transfer Level (RTL),… more
    Google (12/11/25)
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  • Principal Digital Verification

    Northrop Grumman (Linthicum Heights, MD)
    …transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. + Development of ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...(SAP). + 3 years of experience with FPGA or ASIC verification using UVM + Experience developing… more
    Northrop Grumman (10/03/25)
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