- Meta (Menlo Park, CA)
- … to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with ... **Summary:** Meta is hiring ASIC Design Verification Engineer within...**Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC … more
- Meta (Sunnyvale, CA)
- … to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a agile team working with ... **Summary:** Meta is hiring ASIC Design Verification Engineer within...**Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC … more
- Capgemini (Santa Clara, CA)
- …the job you're considering** Join a collaborative and forward-thinking team as a Design Verification Engineer , contributing to the validation of advanced ... environments using SystemVerilog and UVM for IP and SoC designs. + Develop test plans and coverage metrics...or equivalent, with 7 years of experience in pre-silicon design verification . + Expertise in SystemVerilog, UVM,… more
- Meta (Sunnyvale, CA)
- …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Evaluate, develop and drive ... PCIe/Ethernet/DDR, computer architecture and NOC. 4. Define and implement IP/ SoC verification plans, build verification ...based on verification test plan. 6. Drive Design Verification to closure based on defined… more
- Meta (Sunnyvale, CA)
- …on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification plans, ... build verification test benches to enable block/IP/sub-system/ SoC level verification . 2. Develop functional tests...based on verification test plan. 3. Drive Design Verification to closure based on defined… more
- Microsoft Corporation (Redmond, WA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Design Verification Engineer ** to join the team. **Responsibilities** + ... Establish yourself as an integral member of a design verification team for the development of...base other complex IP/blocks or subsystems. + Experience with IP/ SOC verification for a full product cycle… more
- Meta (Sunnyvale, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1....UVM methodology 10. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM… more
- Meta (Sunnyvale, CA)
- …look at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work ... state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine... SOC environments 7. Develop and drive continuous Design Verification improvements using the latest … more
- Qualcomm (San Diego, CA)
- …develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip ... a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you...**Qualifications:** Minimum Experience Level should be 2+ years in SOC -level or core-level verification with good understanding… more
- Meta (Madison, WI)
- …on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification plans, build ... design quality. 3. Develop and drive continuous Design Verification improvements using the latest ...Testbench 9. 3. IP/ SoC (System On Chip) Verification 10. 4. Debugging design 11. 5.… more
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