• FPGA Design Engineer Staff

    Lockheed Martin (Orlando, FL)
    …and Design lead experience \- Experience with Microchip \(MicroSemi\)and Libero SoC Design toolsets \- Familiarity with FPGA Vivado/Vitis toolsets \- ... FPGA validation \- Experience in ASIC / FPGA life cycle \(architecture, design , simulation, verification , validation, integration & test\), particularly at MFC… more
    Lockheed Martin (08/28/25)
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  • ASIC/FPGA Design Engineer (SMES)

    L3Harris (Camden, NJ)
    …and cyber domains in the interest of national security. Job Title: ASIC/FPGA Design Engineer (SMES) Job Code: 29446 Job Location: Camden, NJ Schedule: 9/80 Regular ... Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for...Lint) + Generate test plans + Perform module level verification , synthesis/STA, Lab debug, SW driven validation on Linux… more
    L3Harris (10/12/25)
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  • FPGA Digital Design Engineer 3/4

    Northrop Grumman (Los Angeles, CA)
    …with VHDL within the past 3 years . Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs . Experience with Electronic Design Automation (EDA) Tools: Vivado ... making history. Northrop Grumman Advanced Weapons has an opening for a FPGA Digital Design Engineer with an active clearance, to join our team of qualified, diverse… more
    Northrop Grumman (09/27/25)
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  • Senior DV Engineer

    Capgemini (Santa Clara, CA)
    …more areas-Ethernet, Mixed Signal Digital design verification , Formal Property Verification (Jasper or similar tools), or ARM-based SoC verification . ... **About the Job You're Considering** We're seeking a ** Design Verification Engineer** for a **hybrid...subsystem, and SoC . + Collaborate closely with logic designers to debug failures and resolve design… more
    Capgemini (11/14/25)
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  • Silicon Architect, Reality Labs

    Meta (San Diego, CA)
    …Work cross-functionally with SoC and IP architecture, performance/power modeling, logic design and verification , physical implementation, firmware, CAD, ... Architect who will collaborate with a world-class group of SoC and IP architects, modeling, development, and validation teams,... design issues 9. Hands-on experience in digital design , logic simulation, and performance analysis **Preferred… more
    Meta (10/20/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    … synthesis, and timing analysis of several modules. + Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up ... Science and related (or equivalent experience) + 5+ years of SoC design /integration experience, including architecture and implementation of system-level… more
    NVIDIA (09/30/25)
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  • Senior Embedded Software Engineer

    LOC Performance Products, Inc (Auburn Hills, MI)
    …Model-Based Software Development. + Support of x86, Arm, CPU, GPU, FPGA, and SOC integration using design tools. + Experience with electrical communication ... and requirements management. + Develop software requirement specifications, algorithms, logic flowcharts, activity diagrams, and leverage SysML Modeling and...of Git, Yocto, ) + Support of FPGA and SoC designs using design tools + Support… more
    LOC Performance Products, Inc (11/14/25)
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  • Sr. FPGA Engineer (Starshield)

    SpaceX (Hawthorne, CA)
    …digital designs + Experience in different stages of FPGA development: RTL design , verification , synthesis, timing analysis, lab bring up/validation + Experience ... As an Sr. FPGA engineer on the satellite digital design team, you will be designing, developing, and testing...integrating logic onto SoC platforms and designing high-throughput… more
    SpaceX (09/30/25)
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  • Senior Silicon Bringup and Test Lead, Raxium

    Google (Fremont, CA)
    …+ 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/ SoC ) design , with a focus on both digital logic design and ... experience. + 10 years of experience in analog circuit design , including simulation and verification . + Experience...of the Design -for-Test (DFT) plan. + Architect, design , and implement digital logic utilizing verilog… more
    Google (11/22/25)
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  • FPGA DSP Firmware Engineer

    Leidos (Arlington, VA)
    …(> 20GHz) design techniques * ARM or RISC-V embedded processor based SoC design experience * Proven experience in the military/aerospace hi reliability ... languages, HDL (VHDL, Verilog) and/or MATLAB model(s). * Ability to perform design constraints generation and verification as well as evaluate synthesis… more
    Leidos (10/28/25)
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