- NVIDIA (Santa Clara, CA)
- …design of CPU on-chip interconnect network and last-level caches, working on implementation , synthesis and timing closure while collaborating closely with the logic ... is preferred. + Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. + Strong… more
- Amazon (San Diego, CA)
- …the block meets DFT, timing and power targets by working closely with the implementation team . Learn about requirements and solutions for systems operating in space ... . Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a US citizen or national, US permanent… more