- NVIDIA (Santa Clara, CA)
- …Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working ... our CPU team, you'll be a liaison between Logic design and Physical design teams...expertise is preferred as is a deep understanding of ASIC design flow including RTL design… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design … more
- Cisco (Maynard, MA)
- …or Electrical Engineering and 4+ years of related experience * Hands-on experience in ASIC physical design and implementation * Experience with place & ... working in a smaller ASIC team can provide. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to… more
- Teradyne (North Reading, MA)
- …+ Experience in logic design writing RTL in Verilog HDL + Experience with physical design tools from FPGA vendors (Vivado and/or Quartus) + Ability to debug ... and delivers better business results. Opportunity Overview Our Logic Design Engineering team is seeking a digital logic Verification...Verification Engineer who preferably also has experience in FPGA design . + The primary focus of the role will… more
- SpaceX (Sunnyvale, CA)
- Sr . ASIC Design Engineer...and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer/ Senior : $170,000.00 - ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON...Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check) +… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN VERIFICATION ENGINEER...and weekends as needed COMPENSATION & BENEFITS: Pay range: Design Verification Engineer / Senior : $160,000.00 - $220,000.00/per… more
- Amazon (Sunnyvale, CA)
- …party IP blocks -Estimate power, performance, and area for significant IPs early in design cycle -Execute on design specifications to deliver high quality RTL ... that have gone to volume production -Hands on experience in low power design techniques -Strong written and verbal skills Preferred Qualifications -Master's or Ph.D… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT,… more
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