• Senior Digital Verification

    Huntington Ingalls Industries (Roanoke, VA)
    …Engineering, Computer Science, or a related field * Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, ... short video: https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies...etc. * UVM concepts * Directed, constrained-random, and assertion-based … more
    Huntington Ingalls Industries (07/09/25)
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  • Staff Lead Design Verification

    Northrop Grumman (Annapolis Junction, MD)
    …engineers to make these technologies a reality. **What You'll Get To Do:** As a Digital Verification Lead Engineer , you will have an opportunity to be ... Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and...comprehensive test-benches for behavioral simulation + Design and implement verification strategies for complex digital systems +… more
    Northrop Grumman (07/18/25)
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  • Principal / Senior Principal FPGA/ASIC…

    Northrop Grumman (Annapolis Junction, MD)
    …Sr. Principal level. Qualifications for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a ... Top Secret/SCI security clearance with Polygraph** **.** **Basic Qualifications Senior Principal Digital Verification Engineer :** + Bachelor's degree in a… more
    Northrop Grumman (08/08/25)
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  • Wireless Modem Verification Engineer

    SpaceX (Irvine, CA)
    Wireless Modem Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. WIRELESS MODEM VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're...capabilities of the Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC verification at block and system… more
    SpaceX (09/02/25)
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  • Silicon Verification Engineer

    ManpowerGroup (Mountain View, CA)
    Our client, a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As a Silicon Verification Engineer , you ... mindset, which will align successfully in the organization. **Job Title:** Silicon Verification Engineer **Location:** Mountain View, CA **What's the Job?** +… more
    ManpowerGroup (08/20/25)
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  • Senior Principal FPGA Verification

    BAE Systems (Westminster, CO)
    …may be available based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR** EEO Career Site ... used across multiple projects. + Work in a System Verilog/ UVM environment developing tests, testbenches, UVM components,...(eg Ruby, Python, TCL). + Experience in documentation and verification of high-speed digital electronics, FPGAs, and… more
    BAE Systems (09/09/25)
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  • Senior Quantum Engineer - Cryo-CMOS…

    Microsoft Corporation (Redmond, WA)
    …and Low Power Verification . + Define and implement efficient UVM -based verification environments and use them to verify+test digital designs + Test plan, ... the world. We are looking for a **Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design** ....+ Knowledge of verification principles, testbenches, Universal Verification Methodology ( UVM ), and coverage. + Experience… more
    Microsoft Corporation (09/06/25)
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  • Senior ASIC Verification Engineer

    Tarana Wireless (Milpitas, CA)
    …will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate to solve ... as Python What You'll Need: + BSEE required/MSEE preferred + 5-12 years of related Verification experience + Strong knowledge of UVM + Proficiency with at least… more
    Tarana Wireless (06/26/25)
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  • Lead E/E & Semiconductor Engineer - SOC…

    Capgemini (Seattle, WA)
    **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal candidate ... flows. **Preferred Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in… more
    Capgemini (07/15/25)
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  • ASIC/FPGA Lead Verification Engineer

    Lockheed Martin (Denver, CO)
    **Description:** Join Our Team as an **ASIC & FPGA Lead Verification Engineer ** where you will support over 50 different programs and research and development ... seeking a highly talented and motivated **ASIC & FPGA Verification Engineer ** who has a passion for...for a given design\. * Use SystemVerilog and Universal Verification Methodology \( UVM \) to verify a design… more
    Lockheed Martin (07/12/25)
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