- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This ... variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence Checking + Prior ... are excited to welcome highly talented hardware designers and application engineers to join our Cadence North America Field...companies in the world. Through Cadence's Electronic Design Automation ( EDA ) products, we've worked with a wide range of… more
- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power...**Programming & Scripting:** Proficiency in TCL/TK, Perl scripting. + ** EDA Tools:** Familiarity with Cadence, Synopsys digital flow include… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior DFX Software Engineer - Machine Learning. Do you like to think creatively and enjoy solving challenges that require innovation? If ... software to enable design and development of efficient test pattern generation, application of these patterns on Silicon, failure analysis, and yield learning +… more
- SanDisk (Milpitas, CA)
- …you'll be at the center of innovation. We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory Design team. This is a great ... RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT , timing analysis and closure + Balance design trade-offs with modularity,… more
- Arrow Electronics (San Jose, CA)
- **Position:** Physical Design Engineer (Einfochips Inc) **Job Description:** **What candidate will Be Doing:** + Netlist to-GDSII implementation, including top-level ... interfaces like DDR and PCIe. + Collaborate cross-functionally with RTL, STA, DFT , verification, and packaging teams to ensure smooth integration and closure. +… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Amazon (Austin, TX)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... performance at low cost. You'll provide leadership in the application of new technologies to large scale deployments in...- Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies… more
Locations:
California,
Texas